{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:41:46Z","timestamp":1761324106660},"reference-count":24,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,6]]},"DOI":"10.1109\/hpsr.2017.7968673","type":"proceedings-article","created":{"date-parts":[[2017,7,7]],"date-time":"2017-07-07T18:28:15Z","timestamp":1499452095000},"page":"1-7","source":"Crossref","is-referenced-by-count":10,"title":["Architecture of a synchronized low-latency network node targeted to research and education"],"prefix":"10.1109","author":[{"given":"Christian","family":"Liss","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marian","family":"Ulbricht","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Umar Farooq","family":"Zia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hartmut","family":"Muller","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Altera for Arista 7124FX Platform","year":"2012","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TE.2008.919664"},{"key":"ref12","first-page":"160","author":"lockwood","year":"2007","journal-title":"NetFPGA - An Open Platform for Gigabitrate Network Switching and Routing"},{"key":"ref13","first-page":"1","author":"kay","year":"2009","journal-title":"Pragmatic Network Latency Engineering Fundamental Facts and Analysis cPacket Networks White Paper"},{"journal-title":"Characterizing the Real-Time Behavior of Prioritized Switched-Ethernet 2nd RTLIA","year":"2003","author":"pedreiras","key":"ref14"},{"journal-title":"Implementing zFilter based Forwarding Node on a NetFPGA","year":"2009","author":"kein\u00e4nen","key":"ref15"},{"key":"ref16","first-page":"1","author":"naous","year":"2008","journal-title":"NetFPGA Reusable Router Architecture for Experimental Research"},{"key":"ref17","first-page":"1","author":"naous","year":"2008","journal-title":"Implementing an OpenFlow Switch on the NetFPGA platform"},{"journal-title":"The Axon Network Device Prototyping with NetFPGA","year":"0","author":"shafer","key":"ref18"},{"key":"ref19","first-page":"1","author":"okafor","year":"2015","journal-title":"Harnessing FPGA Processor Cores in Evolving Cloud Based Datacenter Network Designs (DCCN)"},{"journal-title":"Nallatech","year":"0","key":"ref4"},{"journal-title":"Mellanox","year":"0","key":"ref3"},{"key":"ref6","first-page":"68","author":"lockwood","year":"2015","journal-title":"Implementing Ultra Low Latency Data Center Services with Programmable Logic"},{"journal-title":"SMARTzynq Module 5 Port Gigabit Ethernet Industrial Embedded Switch Module","year":"2017","key":"ref5"},{"journal-title":"AMBA AXI4-Stream Protocol Specification","article-title":"ARM","year":"2010","key":"ref8"},{"journal-title":"Linux Base Driver for the Intel Ethernet 10 Gigabit PCI Express Family of Adapters","year":"2013","key":"ref7"},{"journal-title":"NetFPGA - An Open Platform for Gigabitrate Network Switching and Routing","year":"2007","author":"lockwood","key":"ref2"},{"journal-title":"InnoRoute FlowEngine IP-Core","year":"0","key":"ref1"},{"key":"ref9","first-page":"117","author":"pfaff","year":"2015","journal-title":"The Design and Implementation of Open vSwitch"},{"journal-title":"Field-Programmable Gate Array Architectures and Algorithms Optimized for Implementing Datapath Circuits Library and Archives Canada = Bibliothèque et Archives Canada","year":"2005","author":"ye","key":"ref20"},{"key":"ref22","first-page":"1014","author":"moadeli","year":"2007","journal-title":"An Analytical Performance Model for the Spidergon NoC"},{"key":"ref21","first-page":"33","author":"de","year":"2001","journal-title":"Powering Networks on Chips Energy Efficient and Reliable interconnect design for SoCs"},{"journal-title":"Design of all programmable innovation platform for software defined networking Power 75(91W) 21W","year":"2014","author":"hu","key":"ref24"},{"journal-title":"Data-Plane Development Kit","year":"2017","key":"ref23"}],"event":{"name":"2017 IEEE 18th International Conference on High Performance Switching and Routing (HPSR)","start":{"date-parts":[[2017,6,18]]},"location":"Campinas, SP, Brazil","end":{"date-parts":[[2017,6,21]]}},"container-title":["2017 IEEE 18th International Conference on High Performance Switching and Routing (HPSR)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7959756\/7968670\/07968673.pdf?arnumber=7968673","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,7,21]],"date-time":"2017-07-21T05:38:03Z","timestamp":1500615483000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7968673\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,6]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/hpsr.2017.7968673","relation":{},"subject":[],"published":{"date-parts":[[2017,6]]}}}