{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T00:54:41Z","timestamp":1725497681165},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,4]]},"DOI":"10.1109\/hst.2018.8383908","type":"proceedings-article","created":{"date-parts":[[2018,6,14]],"date-time":"2018-06-14T23:36:11Z","timestamp":1529019371000},"page":"167-172","source":"Crossref","is-referenced-by-count":1,"title":["Hardware virtualization for protection against power analysis attack"],"prefix":"10.1109","author":[{"given":"Kai","family":"Yang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jungmin","family":"Park","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mark","family":"Tehranipoor","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2017.2679183"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2015.49"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1214\/aoms\/1177729694"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"529","DOI":"10.1007\/11935308_38","article-title":"Threshold Implementations Against Side-Channel Attacks and Glitches","author":"nikova","year":"2006","journal-title":"International Conference on Information and Communications Security"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2012.6224321"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/11605805_13"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JIOT.2017.2703088"},{"key":"ref9","first-page":"158","article-title":"A Testing Methodology for Side-Channel Resistance Validation","author":"goodwill","year":"2011","journal-title":"NIST Non-invasive Attack Testing Workshop"},{"journal-title":"Field Programmable Gate Array (FPGA) Market Analysis","year":"2016","author":"research","key":"ref1"}],"event":{"name":"2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)","start":{"date-parts":[[2018,4,30]]},"location":"Washington, DC","end":{"date-parts":[[2018,5,4]]}},"container-title":["2018 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8369415\/8383882\/08383908.pdf?arnumber=8383908","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,7,3]],"date-time":"2018-07-03T01:31:32Z","timestamp":1530581492000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8383908\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/hst.2018.8383908","relation":{},"subject":[],"published":{"date-parts":[[2018,4]]}}}