{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,26]],"date-time":"2025-12-26T07:05:23Z","timestamp":1766732723643,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,5]]},"DOI":"10.1109\/i2mtc.2014.6860842","type":"proceedings-article","created":{"date-parts":[[2014,7,29]],"date-time":"2014-07-29T21:02:35Z","timestamp":1406667755000},"page":"747-751","source":"Crossref","is-referenced-by-count":13,"title":["Subpicosecond-resolution time-to-digital converter with multi-edge coding in independent coding lines"],"prefix":"10.1109","author":[{"given":"Ryszard","family":"Szplet","sequence":"first","affiliation":[]},{"given":"Dominik","family":"Sondej","sequence":"additional","affiliation":[]},{"given":"Grzegorz","family":"Grzeda","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"13","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1088\/0957-0233\/20\/2\/025108","article-title":"A 45 ps time digitizer with two-phase clock and dual-edge two-stage interpolation in FPGA device","volume":"20","author":"szplet","year":"2009","journal-title":"Measurement Sci Technology"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1088\/0022-3735\/20\/11\/005"},{"journal-title":"Spartan-6 FPGA Configurable Logic Block User Guide","year":"2010","key":"12"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/IMTC.2010.5488103"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1088\/0026-1394\/41\/1\/004"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1088\/0957-0233\/24\/3\/035904"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1016\/0029-554X(70)90095-9"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/NSSMIC.2008.4775079"},{"key":"6","first-page":"3","article-title":"Identification of the dynamic parameters of fast carry chains and global clock networks in Spartan-6 FPGA device","volume":"59","author":"kwiatkowski","year":"2013","journal-title":"Measurement Automation and Monitoring"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/4.231325"},{"key":"4","article-title":"Design, modeling and testing of data converters","author":"carbone","year":"2014","journal-title":"Chapter VII Time-to-digital Converters"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/NoMeTDC.2013.6658234"},{"key":"8","first-page":"6","author":"wu","year":"0","journal-title":"Several Key Issues on Implementing Delay Line Based TDCs Using FPGAs"}],"event":{"name":"2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)","start":{"date-parts":[[2014,5,12]]},"location":"Montevideo, Uruguay","end":{"date-parts":[[2014,5,15]]}},"container-title":["2014 IEEE International Instrumentation and Measurement Technology Conference (I2MTC) Proceedings"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6845396\/6860504\/06860842.pdf?arnumber=6860842","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,22]],"date-time":"2017-06-22T17:32:15Z","timestamp":1498152735000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6860842\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,5]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/i2mtc.2014.6860842","relation":{},"subject":[],"published":{"date-parts":[[2014,5]]}}}