{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T18:13:19Z","timestamp":1730225599035,"version":"3.28.0"},"reference-count":18,"publisher":"IEEE","license":[{"start":{"date-parts":[[2022,5,16]],"date-time":"2022-05-16T00:00:00Z","timestamp":1652659200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,5,16]],"date-time":"2022-05-16T00:00:00Z","timestamp":1652659200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2022,5,16]]},"DOI":"10.1109\/i2mtc48687.2022.9806688","type":"proceedings-article","created":{"date-parts":[[2022,6,30]],"date-time":"2022-06-30T19:42:14Z","timestamp":1656618134000},"page":"1-6","source":"Crossref","is-referenced-by-count":0,"title":["Hybrid Successive Subtraction Method of Analog to Digital Converter"],"prefix":"10.1109","author":[{"given":"Suchitra","family":"Padidala","sequence":"first","affiliation":[{"name":"IIT Madras,Department of Electrical Engineering,India,600036"}]},{"given":"Nimal J.","family":"Kumar","sequence":"additional","affiliation":[{"name":"IIT Madras,Department of Electrical Engineering,India,600036"}]},{"given":"Jagadeesh Kumar","family":"V","sequence":"additional","affiliation":[{"name":"IIT Madras,Department of Electrical Engineering,India,600036"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Multiple Slope Analog-to-Digital Converter","author":"bondzeit","year":"1971","journal-title":"U S Patent"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"2155","DOI":"10.1109\/TIM.2015.2390957","article-title":"Digital Converter for a contactless displacement sensor","volume":"64","author":"supriya","year":"2015","journal-title":"IEEE Tram Instrum Meas"},{"key":"ref12","first-page":"1","article-title":"An overview of sigma-delta ADCs and DACs","author":"stewart","year":"1995","journal-title":"IEE Colloquium on Oversampling and Sigma-delta Strategies for DSP"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2005.856282"},{"key":"ref14","article-title":"A new algorithm for an incremental sigma-delta converter reconstruction filter","author":"li","year":"2019","journal-title":"32nd Symposium on Integrated Circuits and Systems Design (SBCCI)"},{"key":"ref15","first-page":"447","article-title":"Successive subtraction method of analog to digital conversion","author":"modi","year":"1991","journal-title":"Proc of the International on Instrumentation and Control"},{"key":"ref16","first-page":"36","article-title":"Implementation of an 8-bit succesive subtraction method of ADC","author":"sinha","year":"2017","journal-title":"IEEE Instrumentation & Measurement Magazine"},{"year":"0","key":"ref17","article-title":"LTSPICE&#x2013;&#x201C;Benefits of using LTspice"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/CCAA.2016.7813861"},{"key":"ref4","article-title":"Flash ADC","author":"sutardja","year":"2007","journal-title":"U S Patent"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/49.761034"},{"key":"ref6","article-title":"ADC architectures II: successive approximation ADCs","author":"kester","year":"0","journal-title":"Analog Devices-MTO06 Tutorial"},{"journal-title":"Understanding flash ADCs","year":"0","key":"ref5"},{"key":"ref8","article-title":"A 0.5V 1.1 Msa\/sec 6.3 fJ \/ conversion-step SAR-ADC with tri-level comparator in 40nm CMOS","author":"shikata","year":"2011","journal-title":"IEEE Symposium on VLSI Circuits (VLSI Cir )"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858372"},{"key":"ref2","article-title":"Which ADC architecture is right for your application?","volume":"39","author":"kester","year":"2005","journal-title":"Analog Dialogue"},{"key":"ref1","first-page":"268","article-title":"Sampling and analog-to-digital conversion","author":"lathi","year":"2013","journal-title":"Modern Analog and Digital Communication Systems"},{"key":"ref9","article-title":"A 0.44 fJ \/ conversion-step 11b 600 ksa\/s SAR ADC with semi-resting DAC","author":"sung-en","year":"2016","journal-title":"IEEE Symposium on VLSI Circuits"}],"event":{"name":"2022 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)","start":{"date-parts":[[2022,5,16]]},"location":"Ottawa, ON, Canada","end":{"date-parts":[[2022,5,19]]}},"container-title":["2022 IEEE International Instrumentation and Measurement Technology Conference (I2MTC)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9806445\/9806446\/09806688.pdf?arnumber=9806688","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,25]],"date-time":"2022-07-25T20:17:39Z","timestamp":1658780259000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9806688\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,5,16]]},"references-count":18,"URL":"https:\/\/doi.org\/10.1109\/i2mtc48687.2022.9806688","relation":{},"subject":[],"published":{"date-parts":[[2022,5,16]]}}}