{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T18:36:59Z","timestamp":1730227019820,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2013,8]]},"DOI":"10.1109\/ic3.2013.6612187","type":"proceedings-article","created":{"date-parts":[[2013,10,1]],"date-time":"2013-10-01T18:38:09Z","timestamp":1380652689000},"page":"186-191","source":"Crossref","is-referenced-by-count":2,"title":["A novel, high performance and power efficient implementation of 8×8 multiplier unit using MT-CMOS technique"],"prefix":"10.1109","author":[{"given":"N.","family":"Rajput","sequence":"first","affiliation":[]},{"given":"M.","family":"Sethi","sequence":"additional","affiliation":[]},{"given":"P.","family":"Dobriyal","sequence":"additional","affiliation":[]},{"given":"K.","family":"Sharma","sequence":"additional","affiliation":[]},{"given":"G.","family":"Sharma","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TENCON.2008.4766689"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/IAdCC.2013.6514453"},{"journal-title":"Low Power Sequential Elements for Multimedia and Wireless Communication Applications","year":"2012","author":"kousalya","key":"13"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/4.400426"},{"key":"11","first-page":"2313","article-title":"A pipelined bit serial complex multiplier using distributed arithmetic","author":"he","year":"1995","journal-title":"Proceedings IEEE International Symposium on Circuits and Systems"},{"key":"12","article-title":"Implementation of an efficient Multiplier based on Vedic mathematics using EDA tools","volume":"1","author":"mehta","year":"2012","journal-title":"International Journal of Engineering and Advanced Technology (IJEAT) ISSN 2249-8958"},{"key":"3","first-page":"38","article-title":"High speed low power complex multiplier design using parallel adders and subtractors","volume":"7","author":"saha","year":"2009","journal-title":"International Journal on Electronic and Electrical Engineering (JEEE)"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ACTEA.2009.5227842"},{"journal-title":"Vedic Mathematics or Sixteen Simple Mathematical Formulae from the Veda","year":"1965","author":"swami","key":"1"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.5121\/ijcnc.2010.2405"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2008.4815685"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1964.263830"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ACT.2009.162"},{"key":"4","first-page":"2313","article-title":"A pipelined bit-serial complex multiplier using distributed arithmetic","author":"he","year":"1995","journal-title":"Proceedings IEEE International Symposium on Circuits and Systems"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ISMVL.1999.779717"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2005.51"}],"event":{"name":"2013 Sixth International Conference on Contemporary Computing (IC3)","start":{"date-parts":[[2013,8,8]]},"location":"Noida, India","end":{"date-parts":[[2013,8,10]]}},"container-title":["2013 Sixth International Conference on Contemporary Computing (IC3)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6595807\/6612154\/06612187.pdf?arnumber=6612187","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,22]],"date-time":"2017-03-22T17:46:21Z","timestamp":1490204781000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6612187\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,8]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/ic3.2013.6612187","relation":{},"subject":[],"published":{"date-parts":[[2013,8]]}}}