{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,4,26]],"date-time":"2025-04-26T05:05:31Z","timestamp":1745643931110},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,10]]},"DOI":"10.1109\/ic3ina.2016.7863017","type":"proceedings-article","created":{"date-parts":[[2017,2,27]],"date-time":"2017-02-27T21:30:06Z","timestamp":1488231006000},"page":"23-27","source":"Crossref","is-referenced-by-count":5,"title":["Performance evaluation of Stratix V DE5-Net FPGA board for high performance computing"],"prefix":"10.1109","author":[{"given":"Iman","family":"Firmansyah","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yoshiki","family":"Yamaguchi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Taisuke","family":"Boku","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"DE5-Net User Manual","year":"0","key":"ref10"},{"journal-title":"Stratix V Avalon-MM Interface for PCIe Solutions User Guide","year":"0","key":"ref11"},{"journal-title":"PCI Express High Performance Reference Design","year":"0","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2015.02.005"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2014.92"},{"journal-title":"S5-PCIe-HQ FPGA board","year":"0","key":"ref15"},{"journal-title":"PCIe385-A7\/D5 FPGA board","year":"0","key":"ref16"},{"journal-title":"Altera FFT (1D) Design Example","year":"0","key":"ref17"},{"article-title":"Design and Implementation of a Heterogeneous Highperformance Computing Framework using Dynamic and Partial Reconfigurable FPGAs","year":"0","author":"zhang","key":"ref4"},{"year":"0","key":"ref3","article-title":"FPGA-Accelerator Research Infrastructure Cloud (FAbRIC)"},{"article-title":"High-performance Dynamic Programming on FPGAs with OpenCL","year":"0","author":"settle","key":"ref6"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/Trustcom.2015.634"},{"journal-title":"Altera Corporation","year":"2013","key":"ref8"},{"journal-title":"OpenCL - the Open Standard for Parallel Programming of Heterogeneous Systems","year":"0","key":"ref7"},{"key":"ref2","article-title":"How Clean is Your Cloud?","author":"cook","year":"2012","journal-title":"Greenpeace International Amsterdam"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1968613.1968651"},{"journal-title":"The OpenCL Programming Book","year":"2010","author":"tsuchiyama","key":"ref9"}],"event":{"name":"2016 International Conference on Computer, Control, Informatics and its Applications (IC3INA)","start":{"date-parts":[[2016,10,3]]},"location":"Tangerang, Indonesia","end":{"date-parts":[[2016,10,5]]}},"container-title":["2016 International Conference on Computer, Control, Informatics and its Applications (IC3INA)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7838318\/7862985\/07863017.pdf?arnumber=7863017","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,9]],"date-time":"2017-03-09T13:24:40Z","timestamp":1489065880000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7863017\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/ic3ina.2016.7863017","relation":{},"subject":[],"published":{"date-parts":[[2016,10]]}}}