{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,24]],"date-time":"2025-03-24T06:45:51Z","timestamp":1742798751613,"version":"3.28.0"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/icassp.1985.1168513","type":"proceedings-article","created":{"date-parts":[[2005,3,23]],"date-time":"2005-03-23T19:59:53Z","timestamp":1111607993000},"page":"300-303","source":"Crossref","is-referenced-by-count":50,"title":["Systematic approaches to the design of algorithmically specified systolic arrays"],"prefix":"10.1109","volume":"10","author":[{"given":"J.","family":"Fortes","sequence":"first","affiliation":[]},{"given":"K.","family":"Fu","sequence":"additional","affiliation":[]},{"given":"B.","family":"Wah","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"Transformational VLSI Design A Progress Beport","year":"0","author":"nfcetow","key":"ref39"},{"key":"ref38","article-title":"Mapping an Arbitrarily Large QR AJ(p> rithm into a Fixed Siae VLSI Array","author":"moldovan","year":"1984","journal-title":"Proc of 1984 Int'l Conf on Parallel Processing"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1007\/BF02253685"},{"key":"ref32","article-title":"The Design of Optimal Systolic Arrays","volume":"33","author":"li","year":"1084","journal-title":"IEEE Trans on Computers"},{"key":"ref31","first-page":"134","article-title":"Optimal Design of Systolic Amy\" for Processing","author":"li","year":"1983","journal-title":"Proc Workshop on Computer Arch for Pattern Analysis and Image Database"},{"key":"ref30","first-page":"310","article-title":"The Design cC Optinal Systolic Algorithms","author":"li","year":"1983","journal-title":"Proc of Computer Software and Applications Conference"},{"key":"ref37","article-title":"Design of Algorithmically Special teed VLSI Devices","author":"moldovan","year":"1083","journal-title":"Proc 1983 lnt'l Conf Comp Design VLSI tn Computers"},{"journal-title":"Space- Time Domain Expansion Approach to VLSI and its Application to Hierarchical Scene Matching","year":"1983","author":"cheng","key":"ref6a"},{"journal-title":"Partihontng of Algorithms for Fixed Size VLSI Arefctleclures","year":"1083","author":"moldovan","key":"ref36"},{"journal-title":"Proc 7th Conf Pattern Recognition","year":"1984","key":"ref6b"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1983.12532"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1982.1675929"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1016\/0743-7315(85)90029-2"},{"journal-title":"Defi of Electrical Engii\ufffderii^ Systems","year":"1084","author":"nisbida","key":"ref40"},{"key":"ref11","article-title":"Optimal Linear Schedules for the Parallel Efcectstion of Algorithms","author":"fortes","year":"1984","journal-title":"Proc 1984 Conf Parallel Processing"},{"key":"ref12","article-title":"Dynamically Reconfigurable Fault Tolerant Array Processors","author":"fortes","year":"1984","journal-title":"14'th Conf on Fault Tolerant Computing"},{"journal-title":"Gracefully degradable array processors","year":"1984","author":"fortes","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1983.1654264"},{"key":"ref15","article-title":"Pipelining Array Computations for MIMD Parallelism; A Functional Specification","author":"gannon","year":"1082","journal-title":"Proc 1982 Conf Parallel Processing"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-68402-9_24"},{"key":"ref17","article-title":"Computational Arrays for the Discrete Fourier Transform","author":"johnsson","year":"0","journal-title":"COMPCON 81"},{"key":"ref18","article-title":"Towards a Formal Treatment of VLSI Arrays","author":"johnsson","year":"1981","journal-title":"Proc Second Caltech Conf on VLSI"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1984.1172408"},{"key":"ref28","article-title":"Optimizing Synchronous Circuitry by Retim ing","author":"leiserson","year":"1985","journal-title":"Proc Third Caltech Conference on VLSI"},{"key":"ref4","first-page":"31","article-title":"Concurrent Algorithms as Space-Time Recursion Equations","author":"chen","year":"1982","journal-title":"Proc USC Workshop VLSI Modern Signal Process"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/SFCS.1981.34"},{"journal-title":"Unifying VLSI Array Design with Linear Transformations of Space Time","year":"1983","author":"cappello","key":"ref3"},{"journal-title":"Array pipelining algorithms and pipelined array processors","year":"1981","author":"li","key":"ref29"},{"journal-title":"Space-time Algorithms Semantics and Methodology","year":"1983","author":"chen","key":"ref5"},{"journal-title":"Algorithm transformations for parallel processing and VLSI architecture design","year":"1983","author":"fortes","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ARITH.1978.6155768"},{"key":"ref2","first-page":"448","article-title":"Unifying VLSI Array Designs with Geometric Transform motions","author":"cappello","year":"0","journal-title":"1989 Conf on Parallel Processing"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/800015.808186"},{"key":"ref1","article-title":"Optimal Implementations of Flow Grapha ou Synchronous Multiprocessors","author":"barnwell","year":"1983","journal-title":"1988 Astomar Conf Circuits and Systems"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-68402-9_25"},{"journal-title":"Optimization and interconnection complexity for parallel processors sijngle stage networks and decision trees","year":"1980","author":"kuhn","key":"ref20"},{"key":"ref45","article-title":"Dynamic Programming and Transitive Closure on Linear Pipelines","author":"varman","year":"1984","journal-title":"Int'l Conf Parallel Processing"},{"key":"ref22","article-title":"An Algebra for VLSI Algorithm Dastgn","author":"kung","year":"1983","journal-title":"Elliptic Problem Solvers"},{"key":"ref21","article-title":"Transforming Algorithms for Single-Stage and VLSI Architectures","author":"kuhn","year":"1980","journal-title":"Workshop on Interconnection Networks for Parallel and Distributed Processing"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1145\/800015.808184"},{"key":"ref24","article-title":"On Superecomputing with Systolle\/Wavefront Array Processors","volume":"72","author":"kung","year":"1984","journal-title":"Proc IEEE"},{"journal-title":"The Systematic Design of Systolic Arrays","year":"1983","author":"quinton","key":"ref41"},{"key":"ref23","article-title":"From Transversal Filter to VLSI Wavefront Array","author":"kung","year":"1983","journal-title":"Proc Int l Conf VLSI"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.1984.1172406"},{"journal-title":"Area-efficient VLSI computations","year":"1981","author":"lelserson","key":"ref26"},{"key":"ref43","first-page":"440","article-title":"on Mapping Homogeneous Graphs on a Linear Array-Processor Model","author":"ramakrishnan","year":"1983","journal-title":"Proc of 1983 Int'l Conf on Parallel Processing"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MC.1985.1662798"}],"event":{"name":"IEEE International Conference on Acoustics, Speech, and Signal Processing","location":"Tampa, FL, USA"},"container-title":["ICASSP '85. IEEE International Conference on Acoustics, Speech, and Signal Processing"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx6\/8361\/26343\/01168513.pdf?arnumber=1168513","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T23:07:40Z","timestamp":1489446460000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1168513\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":47,"URL":"https:\/\/doi.org\/10.1109\/icassp.1985.1168513","relation":{},"subject":[]}}