{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,20]],"date-time":"2025-11-20T12:15:18Z","timestamp":1763640918074,"version":"3.28.0"},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccad.2004.1382590","type":"proceedings-article","created":{"date-parts":[[2005,2,22]],"date-time":"2005-02-22T20:29:50Z","timestamp":1109104190000},"page":"300-305","source":"Crossref","is-referenced-by-count":31,"title":["Temporal floorplanning using the T-tree formulation"],"prefix":"10.1109","author":[{"family":"Ping-Hung Yuh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chia-Lin Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Yao-Wen Chang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","first-page":"725","article-title":"Temporal floor-planning using 3D-subTCG","author":"yuh","year":"2004","journal-title":"Proc ASP-DAC"},{"journal-title":"XAPP151 Virtex Series Configuration Architecture User Guide V1 5","year":"2000","key":"17"},{"journal-title":"Virtex-II pro platform FPGA user guide","year":"0","key":"18"},{"key":"15","first-page":"1097","article-title":"Compile-time optimization of dynamic hardware reconfigurations","author":"teich","year":"1999","journal-title":"Proc PDPTA"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008155020711"},{"key":"13","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","article-title":"Optimization by simulated annealing","volume":"220","author":"kirkpatrick","year":"1983","journal-title":"Science"},{"journal-title":"Combinatorial Optimization Networks and Matroids","year":"1976","author":"lawler","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1007\/BF03024089"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332401"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.817546"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2001.955047"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2004.1303119"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707891"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2001.915093"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337541"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/54.825678"},{"journal-title":"AT40K05102040AL_Complete","year":"0","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/5.663540"},{"key":"8","first-page":"268","article-title":"An O-tree representation of non-slicing floorplan and its application","author":"gup","year":"1999","journal-title":"Proc DAC"}],"event":{"name":"ICCAD 2004. International Conference on Computer Aided Design","acronym":"ICCAD-04","location":"San Jose, CA, USA"},"container-title":["IEEE\/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9494\/30133\/01382590.pdf?arnumber=1382590","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T16:09:14Z","timestamp":1497629354000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1382590\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/iccad.2004.1382590","relation":{},"subject":[]}}