{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T09:34:03Z","timestamp":1725615243583},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccad.2004.1382676","type":"proceedings-article","created":{"date-parts":[[2005,2,22]],"date-time":"2005-02-22T15:29:50Z","timestamp":1109086190000},"page":"748-751","source":"Crossref","is-referenced-by-count":6,"title":["Hermes: LUT FPGA technology mapping algorithm for area minimization with optimum depth"],"prefix":"10.1109","author":[{"given":"M.","family":"Teslenko","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Dubrova","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.4153\/CJM-1956-045-5"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882119"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/143165.143216"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/966137.966139"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-58419-6_70"},{"key":"14","first-page":"635","article-title":"Power minimization in LUT-based FPGA technology mapping","author":"wang","year":"2001","journal-title":"Proc Asia and South Pacific Design Automation Conf"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276201"},{"key":"12","first-page":"409","article-title":"Dart: Delay and routability driven technology mapping for LUT based FPGAs","author":"lu","year":"1995","journal-title":"Proceedings of the International Conference on Computer Design"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185333"},{"key":"2","doi-asserted-by":"crossref","first-page":"240","DOI":"10.1145\/127601.127672","article-title":"Xmap: a technology mapper for table-lookup field-programmable gate arrays","author":"karplus","year":"1991","journal-title":"28th ACM\/IEEE Design Automation Conference DAC"},{"key":"1","doi-asserted-by":"crossref","first-page":"227","DOI":"10.1145\/127601.127670","article-title":"Chortle-crf: fast technology mapping for lookup table-based FPGAs","author":"francis","year":"1991","journal-title":"28th ACM\/IEEE Design Automation Conference DAC"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1996.568903"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"6","doi-asserted-by":"crossref","first-page":"208","DOI":"10.1145\/157485.164672","article-title":"performance directed technology mapping for look-up table based fpgas","author":"sawkar","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/54.156154"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1991.185335"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1995.241947"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/92.285741"}],"event":{"name":"ICCAD 2004. International Conference on Computer Aided Design","acronym":"ICCAD-04","location":"San Jose, CA, USA"},"container-title":["IEEE\/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9494\/30133\/01382676.pdf?arnumber=1382676","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T12:09:15Z","timestamp":1497614955000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1382676\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/iccad.2004.1382676","relation":{},"subject":[]}}