{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T07:40:08Z","timestamp":1725522008692},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccad.2005.1560045","type":"proceedings-article","created":{"date-parts":[[2005,12,22]],"date-time":"2005-12-22T12:52:37Z","timestamp":1135255957000},"page":"88-93","source":"Crossref","is-referenced-by-count":4,"title":["Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SoCs"],"prefix":"10.1109","author":[{"given":"A.","family":"Sehgal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Chakrabarty","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","first-page":"1196","article-title":"Time\/Area tradeoffs in testing hierarchical SOCs with hard mega-cores","author":"xu","year":"2004","journal-title":"Proc ITC"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1998.743166"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041802"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1023\/A:1016589322936"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1145\/775832.776000"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1023\/A:1014916913577"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.810737"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041747"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2003.1252857"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.834228"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766653"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1268883"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2003.1271095"},{"key":"24","first-page":"273","article-title":"Power constrained test scheduling with dynamically varied TAM","author":"zhao","year":"2003","journal-title":"Proc VTS"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/2.769444"},{"journal-title":"Agilent 93000 Multi-port Testing User Manual Revision 4 0 0","year":"2002","key":"3"},{"journal-title":"Tiger Advanced Digital with Silicon Germanium Technology","year":"0","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2003.818376"},{"journal-title":"Winning in the SOC Market","year":"0","key":"1"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041875"},{"key":"6","first-page":"111","article-title":"A building block BIST methodology for SOC designs: A case study","author":"chickermane","year":"2001","journal-title":"Proc ITC"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/371254.371258"},{"year":"2004","author":"khoche","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041803"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2004.1269215"}],"event":{"name":"ICCAD-2005. IEEE\/ACM International Conference on Computer-Aided Design, 2005.","location":"San Jose, CA"},"container-title":["ICCAD-2005. IEEE\/ACM International Conference on Computer-Aided Design, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10431\/33130\/01560045.pdf?arnumber=1560045","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,14]],"date-time":"2017-03-14T13:48:53Z","timestamp":1489499333000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1560045\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/iccad.2005.1560045","relation":{},"subject":[]}}