{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:12:58Z","timestamp":1729671178498,"version":"3.28.0"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccad.2005.1560066","type":"proceedings-article","created":{"date-parts":[[2005,12,22]],"date-time":"2005-12-22T17:52:37Z","timestamp":1135273957000},"page":"211-216","source":"Crossref","is-referenced-by-count":2,"title":["Physics-based compact modeling for nonclassical CMOS"],"prefix":"10.1109","author":[{"given":"V.P.","family":"Trivedi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.G.","family":"Fossum","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Mathew","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.M.","family":"Chowdhury","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W.","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.O.","family":"Workman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"B.-Y.","family":"Nguyen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"crossref","first-page":"1605","DOI":"10.1109\/16.405274","article-title":"Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully-depleted SOI low-voltage CMOS technology","volume":"42","author":"yeh","year":"1995","journal-title":"IEEE Trans Electron Devices"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2004.841333"},{"journal-title":"Physics and design of nonclassical nanoscale CMOS devices with ultra-thin bodies","year":"2005","author":"trivedi","key":"18"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/16.902730"},{"key":"16","first-page":"437","article-title":"High-performance symmetric-gate and CMOS compatible vt asymmetric-gate FinFET devices","author":"kedzierski","year":"2001","journal-title":"IEDM Tech Dig"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1016\/j.sse.2003.12.030"},{"journal-title":"UFDG MOSFET model user's guide","year":"2005","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2004.825160"},{"key":"12","first-page":"627","article-title":"Sub 30nm multi-bridge-channel MOSFET (MBCFET) with metal gate electrode for ultra high performance application","author":"yoon","year":"2004","journal-title":"IEDM Tech Dig"},{"key":"21","doi-asserted-by":"publisher","DOI":"10.1109\/16.944198"},{"journal-title":"Physical modeling and analysis of carrier confinement and transport in silicon-on-insulator and double-gate CMOS devices and circuits","year":"2002","author":"ge","key":"20"},{"key":"22","doi-asserted-by":"publisher","DOI":"10.1063\/1.357263"},{"key":"23","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2004.1419284"},{"journal-title":"Process-based compact modeling and analysis of silicon-on-insulator CMOS devices and circuits including double-gate MOSFETs","year":"2001","author":"chiang","key":"24"},{"key":"25","doi-asserted-by":"publisher","DOI":"10.1109\/.2005.1469267"},{"key":"26","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2005.856184"},{"key":"27","first-page":"631","article-title":"Device design consideration for ultrathin SOI MOSFETs","author":"doris","year":"2003","journal-title":"IEEE IEDM Tech Dig"},{"key":"28","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2003.1269371"},{"key":"29","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1983.21282"},{"year":"0","key":"3"},{"journal-title":"BSIM Manual","year":"2001","key":"2"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/SOI.2004.1391610"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/101.708477"},{"year":"0","key":"30"},{"key":"7","first-page":"267","article-title":"Extreme scaling with ultra-thin Si channel MOSFETs","author":"doris","year":"2002","journal-title":"IEDM Tech Dig"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2003.816915"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/16.981219"},{"journal-title":"Intel Multi core","year":"0","key":"31"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/MCD.2002.1005646"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/16.887014"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/16.877181"}],"event":{"name":"ICCAD-2005. IEEE\/ACM International Conference on Computer-Aided Design, 2005.","location":"San Jose, CA"},"container-title":["ICCAD-2005. IEEE\/ACM International Conference on Computer-Aided Design, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10431\/33130\/01560066.pdf?arnumber=1560066","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,17]],"date-time":"2017-06-17T01:55:32Z","timestamp":1497664532000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1560066\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/iccad.2005.1560066","relation":{},"subject":[]}}