{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,7]],"date-time":"2025-01-07T05:28:40Z","timestamp":1736227720216,"version":"3.32.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccad.2005.1560100","type":"proceedings-article","created":{"date-parts":[[2005,12,22]],"date-time":"2005-12-22T17:52:37Z","timestamp":1135273957000},"page":"393-397","source":"Crossref","is-referenced-by-count":1,"title":["DiCER: distributed and cost-effective redundancy for variation tolerance"],"prefix":"10.1109","author":[{"family":"Di Wu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"G.","family":"Venkataraman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Jiang Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Quiyang Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Mahapatra","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/43.67789"},{"key":"17","first-page":"3","article-title":"Buffered Steiner trees for difficult instances","volume":"21","author":"alpert","year":"2002","journal-title":"IEEE TCAD"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2005.1560135"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2002.1004589"},{"key":"16","first-page":"1014","article-title":"Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation","volume":"18","author":"chen","year":"1999","journal-title":"IEEE TCAD"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/43.57781"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.159746"},{"key":"11","doi-asserted-by":"crossref","first-page":"196","DOI":"10.1145\/775832.775885","article-title":"Timing optimization of FPGA placement by logic replication","author":"beraudo","year":"2003","journal-title":"DAC"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1145\/1046192.1046200"},{"key":"3","first-page":"309","article-title":"An efficient algorithm for statistical minimization of total power under timing yield constraints","author":"mani","year":"2005","journal-title":"DAC"},{"key":"20","doi-asserted-by":"publisher","DOI":"10.1145\/329166.329208"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996695"},{"key":"1","first-page":"448","article-title":"A methodology to improve timing yield in the presence of process variations","author":"raj","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2003.820527"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/4.918917"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.86"},{"journal-title":"Design and Analysis of Fault-Tolerant Digital Systems","year":"1989","author":"johnson","key":"5"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1065579.1065662"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996785"},{"key":"8","first-page":"18","article-title":"Reducing clock skew variability via cross links","author":"rajaram","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"}],"event":{"name":"ICCAD-2005. IEEE\/ACM International Conference on Computer-Aided Design, 2005.","location":"San Jose, CA"},"container-title":["ICCAD-2005. IEEE\/ACM International Conference on Computer-Aided Design, 2005."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/10431\/33130\/01560100.pdf?arnumber=1560100","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,6]],"date-time":"2025-01-06T18:48:06Z","timestamp":1736189286000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1560100\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iccad.2005.1560100","relation":{},"subject":[]}}