{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T20:15:16Z","timestamp":1730232916453,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,11]]},"DOI":"10.1109\/iccad.2007.4397250","type":"proceedings-article","created":{"date-parts":[[2008,1,9]],"date-time":"2008-01-09T19:22:47Z","timestamp":1199906567000},"page":"99-104","source":"Crossref","is-referenced-by-count":0,"title":["Practical method for obtaining a feasible integer solution in hierarchical layout optimization"],"prefix":"10.1109","author":[{"family":"Xiaoping Tang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Xin Yuan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michael S.","family":"Gray","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"123","article-title":"Minplex - a compactor that minimizes the bounding rectangle and individual rectangles in a layout","author":"lin","year":"1986","journal-title":"Proc Design Automation Conf"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114886"},{"key":"ref12","first-page":"655","article-title":"Technology migration techniques for simplified layouts with restrictive design rules","author":"tang","year":"2006","journal-title":"Proc Int Conf on Computer Aided Design"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1055137.1055172"},{"article-title":"Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optmization","year":"2004","author":"gray","key":"ref4"},{"key":"ref3","first-page":"56","article-title":"A fast minimum layout perturbation algorithm for electromigration reliability enhancement","author":"chen","year":"1997","journal-title":"Proc Int Symp on Defect and Fault Tolerance in VLSI Systems"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369729"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/267665.267701"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1992.279384"},{"key":"ref7","first-page":"903","article-title":"VLSI layout compaction with grid and mixed constraints","volume":"cad 6","author":"lee","year":"1987","journal-title":"IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems"},{"article-title":"Practical method for hierarchical-preserving layout optimization of integrated circuit layout","year":"2003","author":"allen","key":"ref2"},{"year":"0","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1983.1270022"}],"event":{"name":"2007 IEEE\/ACM International Conference on Computer-Aided Design","start":{"date-parts":[[2007,11,4]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2007,11,8]]}},"container-title":["2007 IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4397222\/4397223\/04397250.pdf?arnumber=4397250","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T19:58:08Z","timestamp":1489694288000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4397250\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,11]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iccad.2007.4397250","relation":{},"ISSN":["1092-3152"],"issn-type":[{"type":"print","value":"1092-3152"}],"subject":[],"published":{"date-parts":[[2007,11]]}}}