{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T11:23:45Z","timestamp":1763724225411},"reference-count":37,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,11]]},"DOI":"10.1109\/iccad.2007.4397268","type":"proceedings-article","created":{"date-parts":[[2008,1,9]],"date-time":"2008-01-09T14:22:47Z","timestamp":1199888567000},"page":"212-219","source":"Crossref","is-referenced-by-count":54,"title":["Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs"],"prefix":"10.1109","author":[{"family":"Roshan Weerasekera","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Li-Rong Zheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Dinesh Pamunuwa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hannu Tenhunen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"year":"2007","journal-title":"Micron 128MB SDRAM Part Catalog","key":"ref33"},{"year":"2007","key":"ref32"},{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1109\/JPROC.2006.873612"},{"year":"2004","author":"waiser","journal-title":"Nanoelectronics and Information Technology Advanced Electronic Materials and Novel Devices","key":"ref30"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1109\/IITC.2006.1648629"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1109\/TVLSI.2005.848814"},{"key":"ref35","first-page":"352","article-title":"Accurate a priori signal integrity estimation using a multilevel dynamic interconnect model for deep submicron vlsi design","author":"zheng","year":"2000","journal-title":"Solid-State Circuits Conference 2000 ESSCIRC '00 Proceedings of the 26th European"},{"year":"2007","key":"ref34"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/LED.2005.862693"},{"key":"ref11","first-page":"991","article-title":"A thermally-aware performance analysis of vertically integrated (3-d) processor-memory hierarchy","author":"luca","year":"2006","journal-title":"DAC '06 Proceedings of the 43rd annual conference on Design automation"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/TEPM.2002.807721"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ISCAS.2005.1465243"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/CICC.2006.320948"},{"key":"ref15","article-title":"Advanced Electronic Packaging","author":"ulrich","year":"2005","journal-title":"IEEE Press Series on Microelectronic Systems Series"},{"key":"ref16","article-title":"Stacked package-on-package design guidelines","author":"dreiza","year":"2005","journal-title":"ChipScale Review Amkor Technology Inc"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1143\/JJAP.45.3030"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/TCSII.2006.885073"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/CICC.2005.1568618"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/IITC.2006.1648688"},{"key":"ref28","first-page":"727","article-title":"Full chip thermal analysis of planar (2-d) and vertically integrated (3-d) high performance ics","author":"im","year":"2000","journal-title":"Electron Devices Meeting 2000 IEDM Technical Digest International"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/ISSCC.2004.1332632"},{"key":"ref27","first-page":"269","article-title":"A detailed cost model for concurrent use with hardware\/software co-design","author":"ragan","year":"2002","journal-title":"Design Automation Conference 2002 Proceedings"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/5.929647"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/TED.2005.850641"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1109\/5.362754"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/TCAD.2006.885831"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TCAD.2006.870069"},{"year":"2005","article-title":"The International Technology Roadmap for Semiconductors(ITRS)","key":"ref2"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1115\/1.1839582"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1145\/343647.343813"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/VLSIC.2005.1469403"},{"year":"1990","author":"backoglu","journal-title":"Circuits Interconnections and Packaging for VLSI","key":"ref22"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/ISSCC.2005.1493969"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1109\/92.902259"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1109\/TCS.1979.1084635"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/96.544360"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1007\/978-1-4757-4841-3"}],"event":{"name":"2007 IEEE\/ACM International Conference on Computer-Aided Design","start":{"date-parts":[[2007,11,4]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2007,11,8]]}},"container-title":["2007 IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4397222\/4397223\/04397268.pdf?arnumber=4397268","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T16:38:43Z","timestamp":1489682323000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4397268\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,11]]},"references-count":37,"URL":"https:\/\/doi.org\/10.1109\/iccad.2007.4397268","relation":{},"ISSN":["1092-3152"],"issn-type":[{"type":"print","value":"1092-3152"}],"subject":[],"published":{"date-parts":[[2007,11]]}}}