{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,30]],"date-time":"2026-06-30T03:06:43Z","timestamp":1782788803184,"version":"3.54.5"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,11]]},"DOI":"10.1109\/iccad.2007.4397290","type":"proceedings-article","created":{"date-parts":[[2008,1,9]],"date-time":"2008-01-09T19:22:47Z","timestamp":1199906567000},"page":"354-361","source":"Crossref","is-referenced-by-count":100,"title":["Combinational and sequential mapping with priority cuts"],"prefix":"10.1109","author":[{"given":"Alan","family":"Mishchenko","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Sungmin Cho","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Satrajit Chatterjee","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Robert","family":"Brayton","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1044111.1044121"},{"key":"ref11","first-page":"14","article-title":"Heuristics for area minimization in LUT-based FPGA technology mapping","author":"manohara-rajah","year":"0","journal-title":"Proc IWLS '04"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887925"},{"key":"ref13","article-title":"Integrating logic synthesis, technology mapping, and retiming","author":"mishchenko","year":"2006","journal-title":"ERL Technical Report"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/275107.275118"},{"key":"ref15","first-page":"433","article-title":"Incremental retiming for FPGA physical synthesis","author":"singh","year":"0","journal-title":"Proc DAC'05"},{"key":"ref4","first-page":"68","article-title":"Simultaneous depth and area minimization in LUT-based FPGA mapping","author":"cong","year":"0","journal-title":"Proc FPGA'95"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/92.285741"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382677"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/296399.296425"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/43.329262"},{"key":"ref7","article-title":"Applying logic synthesis to speedup SAT","author":"een","year":"0","journal-title":"Proc SAT'07"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref1","article-title":"ABC: A System for Sequential Synthesis and Verification","year":"0","journal-title":"Release 70319"},{"key":"ref9","year":"0"}],"event":{"name":"2007 IEEE\/ACM International Conference on Computer-Aided Design","location":"San Jose, CA, USA","start":{"date-parts":[[2007,11,4]]},"end":{"date-parts":[[2007,11,8]]}},"container-title":["2007 IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4397222\/4397223\/04397290.pdf?arnumber=4397290","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,16]],"date-time":"2017-03-16T19:24:19Z","timestamp":1489692259000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4397290\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,11]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iccad.2007.4397290","relation":{},"ISSN":["1092-3152"],"issn-type":[{"value":"1092-3152","type":"print"}],"subject":[],"published":{"date-parts":[[2007,11]]}}}