{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,2]],"date-time":"2026-06-02T03:52:28Z","timestamp":1780372348286,"version":"3.54.1"},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,11]]},"DOI":"10.1109\/iccad.2007.4397329","type":"proceedings-article","created":{"date-parts":[[2008,1,9]],"date-time":"2008-01-09T19:22:47Z","timestamp":1199906567000},"page":"590-597","source":"Crossref","is-referenced-by-count":26,"title":["3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits"],"prefix":"10.1109","author":[{"family":"Pingqiang Zhou","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Yuchun Ma","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Zhouyuan Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Robert P.","family":"Dick","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Li Shang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Hai Zhou","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Xianlong Hong","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"family":"Qiang Zhou","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref10","first-page":"341","article-title":"Interconnect characteristics of 2.5D system integration scheme","author":"deng","year":"2001","journal-title":"Proc Int Symp Physical Design"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2004.1329460"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2004.1382591"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2006.77"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2004.1337555"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2003.1257591"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/LPE.2005.195522"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2007.357998"},{"key":"ref18","first-page":"573","article-title":"Engineering details of a stable analytic placer","author":"vorwerk","year":"2004","journal-title":"Proc Int Conf Computer-Aided Design"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1038\/324446a0"},{"key":"ref4","article-title":"Hierarchical 3-D floorplanning algorithm for wirelength optimization","author":"li","year":"2007","journal-title":"IEEE Trans Circuits and Systems I"},{"key":"ref3","article-title":"Design of High-Performance Microprocessor Circuits","author":"chandrakasan","year":"2001"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/43.552084"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1109\/ICCAD.2000.896442","article-title":"Corner block list: An effective and efficient topological representation of non-slicing floorplan","author":"hong","year":"2000","journal-title":"Proc Int Conf Computer-Aided Design"},{"key":"ref8","first-page":"458","article-title":"B*-trees: A new representation for non-slicing floorplans","author":"wu","year":"2000","journal-title":"Proc Design Automation Conf"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/43.703832"},{"key":"ref2","year":"2006"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379062"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2004.1347939"},{"key":"ref20","first-page":"1103","article-title":"Constraint-driven floorplan repair","author":"moffitt","year":"2006","journal-title":"Proc Design Automation Conf"},{"key":"ref22","first-page":"1827","article-title":"The Galvanic circuit investigated mathematically","author":"ohm","year":"0"},{"key":"ref21","first-page":"188","article-title":"A robust detailed placement for mixed-size IC designs","author":"cong","year":"2006","journal-title":"Proc Asia & South Pacific Design Automation Conf"},{"key":"ref24","first-page":"319","article-title":"Efficient full-chip thermal modeling and analysis","author":"li","year":"2004","journal-title":"Proc Int Conf Computer-Aided Design"},{"key":"ref23","article-title":"A high efficiency full-chip thermal simulation algorithm","author":"zhan","year":"2005","journal-title":"Proc Int Conf Computer-Aided Design"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882589"}],"event":{"name":"2007 IEEE\/ACM International Conference on Computer Aided Design","location":"San Jose, CA","start":{"date-parts":[[2007,11,4]]},"end":{"date-parts":[[2007,11,8]]}},"container-title":["2007 IEEE\/ACM International Conference on Computer-Aided Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4397222\/4397223\/04397329.pdf?arnumber=4397329","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,11]],"date-time":"2019-03-11T23:34:41Z","timestamp":1552347281000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/4397329\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,11]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/iccad.2007.4397329","relation":{},"subject":[],"published":{"date-parts":[[2007,11]]}}}