{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,3]],"date-time":"2026-06-03T18:46:14Z","timestamp":1780512374083,"version":"3.54.1"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1109\/iccad.2011.6105405","type":"proceedings-article","created":{"date-parts":[[2011,12,22]],"date-time":"2011-12-22T18:06:43Z","timestamp":1324577203000},"page":"694-701","source":"Crossref","is-referenced-by-count":202,"title":["CACTI-P: Architecture-level modeling for SRAM-based structures with advanced leakage reduction techniques"],"prefix":"10.1109","author":[{"given":"Sheng","family":"Li","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ke","family":"Chen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jung Ho","family":"Ahn","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jay B.","family":"Brockman","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Norman P.","family":"Jouppi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"19","author":"xi","year":"2001","journal-title":"BSIM4 2 1 MOSFET Model"},{"key":"17","author":"weste","year":"2004","journal-title":"CMOS VLSI Design A Circuits and Systems Perspective"},{"key":"18","article-title":"An enhanced access and cycle time model for on-chip cacheS","author":"wilton","year":"1994","journal-title":"DEC WRL Tech Rep Technical Report Number 93\/5"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1145\/1394608.1382127"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034082"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2006.1696062"},{"key":"14","year":"0","journal-title":"Model for Assessment of CMOS Technologies and Roadmaps (MASTAR)"},{"key":"11","doi-asserted-by":"crossref","first-page":"937","DOI":"10.1109\/TVLSI.2004.832939","article-title":"Distributed sleep transistor network for power reduction","volume":"12","author":"long","year":"2004","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2002.808156"},{"key":"3","first-page":"480","author":"anis","year":"2002","journal-title":"Dynamic and Leakage Power Reduction in MTCMOS Circuits Using An Automated Efficient Gate Clustering Technique"},{"key":"20","first-page":"895","article-title":"SRAM design on 65-nm CMOS technology with dynamic sleep transistor for leakage reduction","volume":"40","author":"zhang","year":"2005","journal-title":"JSSC"},{"key":"2","year":"0","journal-title":"McSim A Manycore Simulation Infrastructure"},{"key":"1","year":"0","journal-title":"CACTI 6 5"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"7","doi-asserted-by":"crossref","first-page":"495","DOI":"10.1145\/277044.277180","article-title":"MTCMOS hierarchical sizing based on mutual exclusive discharge patterns","author":"kao","year":"1998","journal-title":"Proceedings 1998 Design and Automation Conference 35th DAC (Cat No 98CH36175) DAC"},{"key":"6","doi-asserted-by":"crossref","DOI":"10.1145\/1241601.1241623","article-title":"Performance counters and development of SPEC CPU2006","volume":"35","author":"henning","year":"2007","journal-title":"Computer Architecture News"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007151"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2007.4425784"},{"key":"9","article-title":"McPAT 1.0: An integrated power, area, and timing modeling framework for multicore architectures","author":"li","year":"2009","journal-title":"HP Labs Tech Rep HPL-2009-206"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2005.35"}],"event":{"name":"2011 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","location":"San Jose, CA, USA","start":{"date-parts":[[2011,11,7]]},"end":{"date-parts":[[2011,11,10]]}},"container-title":["2011 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6095474\/6105287\/06105405.pdf?arnumber=6105405","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T11:43:31Z","timestamp":1497959011000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6105405\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iccad.2011.6105405","relation":{},"subject":[],"published":{"date-parts":[[2011,11]]}}}