{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:33:46Z","timestamp":1773246826889,"version":"3.50.1"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,11]]},"DOI":"10.1109\/iccad.2011.6105409","type":"proceedings-article","created":{"date-parts":[[2011,12,22]],"date-time":"2011-12-22T13:06:43Z","timestamp":1324559203000},"page":"724-731","source":"Crossref","is-referenced-by-count":30,"title":["Gate sizing and device technology selection algorithms for high-performance industrial designs"],"prefix":"10.1109","author":[{"given":"Muhammet Mustafa","family":"Ozdal","sequence":"first","affiliation":[]},{"given":"Steven","family":"Burns","sequence":"additional","affiliation":[]},{"given":"Jiang","family":"Hu","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"17","first-page":"413","article-title":"Power minimization by simultaneous dual-Vth assignment and gate sizing","author":"wei","year":"2000","journal-title":"proc of CICC"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2002.1167564"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2009.2018872"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.895793"},{"key":"14","first-page":"783","article-title":"Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment","author":"srivastava","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2011.5763293"},{"key":"12","article-title":"A network-flow based cell sizing algorithm","author":"ren","year":"2008","journal-title":"Workshop Notes Int'l Workshop on Logic Synthesis"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/43.771182"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1990.114881"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1990.136648"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1145\/1514932.1514940"},{"key":"7","article-title":"A 32nm logic tech. featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171m2 sram cell size in a 291mb array","year":"2008","journal-title":"Proc of IEDM"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/92.645073"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1145\/1120725.1120881"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1145\/1077603.1077642"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1993.393332"},{"key":"8","doi-asserted-by":"crossref","first-page":"818","DOI":"10.1109\/TCAD.2009.2015735","article-title":"Gate sizing for cell-library-based designs","volume":"28","author":"hu","year":"2009","journal-title":"IEEE Trans on Computer-Aided Design"}],"event":{"name":"2011 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","location":"San Jose, CA, USA","start":{"date-parts":[[2011,11,7]]},"end":{"date-parts":[[2011,11,10]]}},"container-title":["2011 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/6095474\/6105287\/06105409.pdf?arnumber=6105409","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T07:43:30Z","timestamp":1497944610000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6105409\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,11]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/iccad.2011.6105409","relation":{},"subject":[],"published":{"date-parts":[[2011,11]]}}}