{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:44:00Z","timestamp":1761648240001,"version":"3.28.0"},"reference-count":31,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/iccad.2014.7001367","type":"proceedings-article","created":{"date-parts":[[2015,1,13]],"date-time":"2015-01-13T20:11:15Z","timestamp":1421179875000},"page":"301-308","source":"Crossref","is-referenced-by-count":17,"title":["Using multi-level cell STT-RAM for fast and energy-efficient local checkpointing"],"prefix":"10.1109","author":[{"given":"Ping","family":"Chi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cong","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tao","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiangyu","family":"Dong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Xie","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref31","DOI":"10.1145\/1555754.1555758"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1145\/2155620.2155642"},{"key":"ref10","article-title":"Novel highly scalable multi-level cell for STT-MRAM with stacked perpendicular MTJs","author":"aoki","year":"2013","journal-title":"Symposium on VLSI Technology"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/ICCAD.2013.6691153"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ICCAD.2011.6105369"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/ISPASS.2013.6557176"},{"key":"ref14","article-title":"Local checkpointing using a multi-level cell","author":"yoon","year":"2013","journal-title":"Patent"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/JSSC.2008.2006439"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/MWSCAS.2010.5548848"},{"key":"ref17","article-title":"Revive: cost-effective architectural support for rollback recovery in shared-memory multiprocessors","author":"prvulovic","year":"2002","journal-title":"ISCA"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/71.730527"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/12.543705"},{"key":"ref28","doi-asserted-by":"crossref","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"Computer Architecture News"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.7873\/DATE.2013.152"},{"key":"ref27","article-title":"Processor caches built using multi-level spin-transfer torque RAM cells","author":"chen","year":"2011","journal-title":"ISLPED"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1145\/1970386.1970387"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1145\/1654059.1654117"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1145\/1186736.1186737"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/MSST.2007.4367962"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/IPDPS.2013.69"},{"key":"ref7","article-title":"De-sign, modeling, and evaluation of a scalable multi-level checkpointing system","author":"moody","year":"2010","journal-title":"SC"},{"year":"2009","author":"amarasinghe","article-title":"Exascale software study: software challenges in extreme scale systems","key":"ref2"},{"year":"2013","author":"zhao","article-title":"Improving phase change memory (PCM) and spin-torque-transfer magnetic-RAM (STT-MRAM) as next-generation memories: a circuit perspective","key":"ref9"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/DSN.2006.5"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/12.142678"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/RELDIS.1992.235144"},{"key":"ref21","article-title":"Evaluation of checkpoint mechanisms for massively parallel machines","author":"chiueh","year":"1996","journal-title":"FTCS"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1145\/1551609.1551619"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1002\/(SICI)1097-024X(199902)29:2<125::AID-SPE224>3.0.CO;2-7"},{"year":"2008","article-title":"International technology roadmap for semiconductors (ITRS) 2008 update","key":"ref26"},{"doi-asserted-by":"publisher","key":"ref25","DOI":"10.1063\/1.3049617"}],"event":{"name":"2014 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","start":{"date-parts":[[2014,11,2]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2014,11,6]]}},"container-title":["2014 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6991350\/7001313\/07001367.pdf?arnumber=7001367","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T03:34:29Z","timestamp":1498188869000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7001367\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":31,"URL":"https:\/\/doi.org\/10.1109\/iccad.2014.7001367","relation":{},"subject":[],"published":{"date-parts":[[2014,11]]}}}