{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T20:06:57Z","timestamp":1730232417612,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/iccad.2014.7001423","type":"proceedings-article","created":{"date-parts":[[2015,1,13]],"date-time":"2015-01-13T20:11:15Z","timestamp":1421179875000},"page":"663-669","source":"Crossref","is-referenced-by-count":0,"title":["Planning and placing power clamps for effective CDM protection"],"prefix":"10.1109","author":[{"family":"Hsin-Chun Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sean S.-Y","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Hung-Ming Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.805720"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105371"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2012.04.021"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TIT.1982.1056489"},{"key":"ref14","first-page":"315","article-title":"A chip-level electrostatic discharge simulation strategy","author":"qian","year":"2004","journal-title":"IEEE\/ACM Proceedings of the International Conference on Computer Aided Design"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2010.5488782"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1002\/0470846054"},{"year":"0","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337541"},{"journal-title":"Method for placing electrostatic discharge clamps within integrated circuit devices","year":"2006","author":"bakir","key":"ref5"},{"key":"ref8","first-page":"1011","article-title":"ESD test methods on integrated circuits: an overview","volume":"2","author":"ker","year":"2001","journal-title":"IEEE Int Conf Electronics Circuits Systems"},{"key":"ref7","first-page":"47","article-title":"ESD-induced internal core device failure: new failure modes in system-on-chip (SOC) designs","author":"huh","year":"2005","journal-title":"International Workshop on System-on-Chip for Real-Time Applications"},{"year":"0","key":"ref2"},{"year":"0","key":"ref1"},{"key":"ref9","first-page":"456","article-title":"Chip-level simulation for CDM failures in multi-power ICs","author":"lee","year":"2000","journal-title":"Electrical Overstress\/Electrostatic Discharge Symposium"}],"event":{"name":"2014 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","start":{"date-parts":[[2014,11,2]]},"location":"San Jose, CA","end":{"date-parts":[[2014,11,6]]}},"container-title":["2014 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6991350\/7001313\/07001423.pdf?arnumber=7001423","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T06:23:55Z","timestamp":1490336635000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7001423\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iccad.2014.7001423","relation":{},"subject":[],"published":{"date-parts":[[2014,11]]}}}