{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T20:06:58Z","timestamp":1730232418105,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,11]]},"DOI":"10.1109\/iccad.2014.7001436","type":"proceedings-article","created":{"date-parts":[[2015,1,13]],"date-time":"2015-01-13T15:11:15Z","timestamp":1421161875000},"page":"758-765","source":"Crossref","is-referenced-by-count":14,"title":["UI-Timer: An ultra-fast clock network pessimism removal algorithm"],"prefix":"10.1109","author":[{"given":"Tsung-Wei","family":"Huang","sequence":"first","affiliation":[]},{"given":"Pei-Ci","family":"Wu","sequence":"additional","affiliation":[]},{"given":"Martin D. F.","family":"Wong","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2560519.2565876"},{"key":"ref11","article-title":"A New Implementation of Yen's Ranking Loopless Paths Algorithm","volume":"1","author":"martins","year":"2003","journal-title":"Journal of Operations Research Quarterly"},{"article-title":"Common Clock Path Pessimism Analysis for Circuit Designs using Clock Tree Networks","year":"2011","author":"ravi","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1287\/mnsc.17.11.712"},{"key":"ref14","first-page":"632","article-title":"General Framework for Removal of Clock Network Pessimism","author":"zejda","year":"2002","journal-title":"Proc IEEE\/ACM ICCAD"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/6617.6621"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1016\/j.artint.2011.07.003"},{"article-title":"Clock-Reconvergence Pessimism Removal in Hierarchical Static Timing Analysis","year":"2013","author":"bhardwaj","key":"ref6"},{"key":"ref5","first-page":"88","article-title":"The LCA problem revisited","volume":"1776","author":"bender","year":"2000","journal-title":"Proceedings of the 4th Latin American Symposium on Theoretical Informatics"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SFCS.1994.365697"},{"article-title":"Static Timing Analysis for Nanometer Designs: A Practical Approach","year":"2009","author":"bhasker","key":"ref7"},{"journal-title":"OpenMP Parallel Programming API","year":"0","key":"ref2"},{"journal-title":"TAU 2014 Contest Pessimism Removal of Timing Analysis","year":"2014","key":"ref1"},{"article-title":"Network Timing Analysis Method which Eliminates Timing Variations between Signals Traversing a Common Circuit Path","year":"1997","author":"hathaway","key":"ref9"}],"event":{"name":"2014 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","start":{"date-parts":[[2014,11,2]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2014,11,6]]}},"container-title":["2014 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6991350\/7001313\/07001436.pdf?arnumber=7001436","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T01:19:52Z","timestamp":1490318392000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7001436\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,11]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iccad.2014.7001436","relation":{},"subject":[],"published":{"date-parts":[[2014,11]]}}}