{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T08:45:10Z","timestamp":1729673110715,"version":"3.28.0"},"reference-count":25,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/iccad.2017.8203753","type":"proceedings-article","created":{"date-parts":[[2017,12,14]],"date-time":"2017-12-14T22:02:04Z","timestamp":1513288924000},"page":"1-8","source":"Crossref","is-referenced-by-count":1,"title":["Leveraging value locality for efficient design of a hybrid cache in multicore processors"],"prefix":"10.1109","author":[{"given":"Mohammad","family":"Arjomand","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Amin","family":"Jadidi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mahmut T.","family":"Kandemir","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chita R.","family":"Das","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2011.5993611"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3143314.3078547"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2420954"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS.2016.79"},{"key":"ref14","first-page":"731","article-title":"An overview of non-volatile memory technology and the implication for tools and architectures","author":"li","year":"2009","journal-title":"DATE"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1669112.1669172"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/237090.237173"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2007.33"},{"key":"ref18","article-title":"A 1.5nsec-2.1nsec random read-write cycle 1Mb STT-RAM using 6T2MTJ cell with background write for nonvolatile e-memories","author":"ohsawa","year":"2013","journal-title":"VLSIT"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2017.8167774"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2658989"},{"key":"ref3","article-title":"Relaxing writes in non-volatile processor cache using frequent value locality","author":"arjomand","year":"2012","journal-title":"DAC (WIP)"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The Gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGArch Computer Architecture News"},{"key":"ref5","volume":"0","author":"bienia","year":"2009","journal-title":"MOBS"},{"key":"ref8","article-title":"NVSim: a circuit-level performance, energy, and area model for emerging nonvolatile memory","volume":"31","author":"dong","year":"2012","journal-title":"IEEE TCAD"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.18"},{"journal-title":"ITRS International Technology Roadmap for Semiconductor","year":"2011","key":"ref2"},{"key":"ref9","first-page":"7","article-title":"Leveraging value locality in optimizing NAND flash-based SSDs","author":"gupta","year":"2011","journal-title":"FAST"},{"journal-title":"Emerging research devices","year":"2011","key":"ref1"},{"key":"ref20","first-page":"1","article-title":"An efficient STT-RAM last level cache architecture for GPUs","volume":"197","author":"samavatian","year":"2014","journal-title":"DAC"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2009.4798259"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1241601.1241625"},{"key":"ref24","first-page":"197","article-title":"Energy efficient frequent value data cache design","author":"yang","year":"2002","journal-title":"Micro"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2155620.2155659"},{"key":"ref25","doi-asserted-by":"crossref","first-page":"264","DOI":"10.1145\/1687399.1687448","article-title":"Hybrid cache architecture with disparate memory technologies","author":"zhou","year":"2009","journal-title":"ICCAD"}],"event":{"name":"2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","start":{"date-parts":[[2017,11,13]]},"location":"Irvine, CA","end":{"date-parts":[[2017,11,16]]}},"container-title":["2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8167715\/8203744\/08203753.pdf?arnumber=8203753","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,29]],"date-time":"2023-08-29T22:53:00Z","timestamp":1693349580000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8203753\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/iccad.2017.8203753","relation":{},"subject":[],"published":{"date-parts":[[2017,11]]}}}