{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,11]],"date-time":"2026-03-11T16:43:40Z","timestamp":1773247420079,"version":"3.50.1"},"reference-count":29,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/iccad.2017.8203767","type":"proceedings-article","created":{"date-parts":[[2017,12,14]],"date-time":"2017-12-14T22:02:04Z","timestamp":1513288924000},"page":"109-116","source":"Crossref","is-referenced-by-count":6,"title":["Sequential engineering change order under retiming and resynthesis"],"prefix":"10.1109","author":[{"given":"Nian-Ze","family":"Lee","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Victor N.","family":"Kravets","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jie-Hong R.","family":"Jiang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391604"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882520"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397285"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/1629911.1630018"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/1687399.1687546"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/BF01759032"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/217474.217604"},{"key":"ref17","author":"lin","year":"2012","journal-title":"Functional Rectification on Sequential Circuits by Liveness Model Checking Techniques"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/43.62793"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2008.ECP.8"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.857396"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.2307\/2963593"},{"key":"ref27","first-page":"729","article-title":"A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques","author":"wu","year":"2010","journal-title":"Proc ICCAD"},{"key":"ref3","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4020-8588-8","author":"coussy","year":"2008","journal-title":"High-Level Synthesis from Algorithm to Digital Circuit"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2010.5653648"},{"key":"ref29","article-title":"Berkeley Logic Synthesis and Verification Group","year":"0","journal-title":"ABC A System for Sequential Synthesis and Verification"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.62792"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1996.545583"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"1723","DOI":"10.1109\/TCAD.2012.2201480","article-title":"TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders","volume":"31","author":"ho","year":"2012","journal-title":"IEEE Trans on CAD"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1999.810642"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/FAMCAD.2007.31"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024757"},{"key":"ref20","article-title":"REVERSE: Efficient Sequential Verification for Retiming","author":"mneimneh","year":"2003","journal-title":"IWLS"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2007.907271"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.209"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024758"},{"key":"ref23","first-page":"226","article-title":"Efficient Implementation of Retiming","author":"shenoy","year":"1994","journal-title":"Proc ICCAD"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/43.811329"},{"key":"ref25","first-page":"1567","article-title":"Multi-Patch Generation for Multi-Error Logic Rectification by Interpolation with Cofactor Reduction","author":"tang","year":"2012","journal-title":"Proc DATE"}],"event":{"name":"2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","location":"Irvine, CA","start":{"date-parts":[[2017,11,13]]},"end":{"date-parts":[[2017,11,16]]}},"container-title":["2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8167715\/8203744\/08203767.pdf?arnumber=8203767","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,10,24]],"date-time":"2020-10-24T09:07:10Z","timestamp":1603530430000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8203767\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/iccad.2017.8203767","relation":{},"subject":[],"published":{"date-parts":[[2017,11]]}}}