{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,4]],"date-time":"2026-04-04T18:11:31Z","timestamp":1775326291242,"version":"3.50.1"},"reference-count":23,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/iccad.2017.8203772","type":"proceedings-article","created":{"date-parts":[[2017,12,14]],"date-time":"2017-12-14T22:02:04Z","timestamp":1513288924000},"page":"147-154","source":"Crossref","is-referenced-by-count":32,"title":["Clepsydra: Modeling timing flows in hardware designs"],"prefix":"10.1109","author":[{"given":"Armaiti","family":"Ardeshiricham","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wei","family":"Hu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ryan","family":"Kastner","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2012.6231062"},{"key":"ref11","article-title":"Register transfer level information flow tracking for provably secure hardware design","author":"ardeshiricham","year":"0","journal-title":"Proceedings of the 2017 Conference on Design Automation & Test in Europe"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/1508244.1508258"},{"key":"ref13","article-title":"Imprecise security: quality and complexity tradeoffs for hardware information flow tracking","author":"hu","year":"0","journal-title":"Proceedings of the 35th international conference on Computer-Aided Design"},{"key":"ref14","year":"0","journal-title":"Yosys Open SYnthesis Suite"},{"key":"ref15","year":"0"},{"key":"ref16","doi-asserted-by":"crossref","DOI":"10.1145\/1273440.1250723","article-title":"New cache designs for thwarting software cache-based side channel attacks","author":"wang","year":"2007","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref17","year":"0"},{"key":"ref18","year":"0"},{"key":"ref19","doi-asserted-by":"crossref","DOI":"10.1145\/2024723.2000087","article-title":"Crafting a usable microkernel, processor, and i\/o system with strict and provable information flow security","author":"tiwari","year":"2011","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref4","author":"percival","year":"2005","journal-title":"Cache missing for fun and profit"},{"key":"ref3","author":"bernstein","year":"2005","journal-title":"Cache-timing attacks on AES"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024782"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.3233\/JCS-1992-13-404"},{"key":"ref8","article-title":"On subnormal floating point and abnormal timing","author":"andrysco","year":"2015","journal-title":"IEEE Symposium on Security and Privacy"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2007.16"},{"key":"ref2","article-title":"A timing attack against rsa with the chinese remainder theorem","author":"schindler","year":"2000","journal-title":"International Workshop on Cryptographic Hardware and Embedded Systems"},{"key":"ref1","article-title":"Timing attacks on implementations of diffie-hellman, rsa, dss, and other systems","author":"kocher","year":"0","journal-title":"Advances in Cryptology-Crypto'98"},{"key":"ref9","doi-asserted-by":"crossref","DOI":"10.1145\/2786763.2694372","article-title":"A hardware design language for timing-sensitive information-flow security","author":"zhang","year":"2015","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2014.2331332"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/2541940.2541947"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/1993498.1993512"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2015.7140256"}],"event":{"name":"2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","location":"Irvine, CA","start":{"date-parts":[[2017,11,13]]},"end":{"date-parts":[[2017,11,16]]}},"container-title":["2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8167715\/8203744\/08203772.pdf?arnumber=8203772","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,25]],"date-time":"2022-01-25T22:47:22Z","timestamp":1643150842000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8203772\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/iccad.2017.8203772","relation":{},"subject":[],"published":{"date-parts":[[2017,11]]}}}