{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,23]],"date-time":"2026-04-23T14:46:11Z","timestamp":1776955571722,"version":"3.51.4"},"reference-count":43,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/iccad.2017.8203780","type":"proceedings-article","created":{"date-parts":[[2017,12,14]],"date-time":"2017-12-14T17:02:04Z","timestamp":1513270924000},"page":"209-216","source":"Crossref","is-referenced-by-count":133,"title":["Reusability is FIRRTL ground: Hardware construction languages, compiler frameworks, and transformations"],"prefix":"10.1109","author":[{"given":"Adam","family":"Izraelevitz","sequence":"first","affiliation":[]},{"given":"Jack","family":"Koenig","sequence":"additional","affiliation":[]},{"given":"Patrick","family":"Li","sequence":"additional","affiliation":[]},{"given":"Richard","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Angie","family":"Wang","sequence":"additional","affiliation":[]},{"given":"Albert","family":"Magyar","sequence":"additional","affiliation":[]},{"given":"Donggyu","family":"Kim","sequence":"additional","affiliation":[]},{"given":"Colin","family":"Schmidt","sequence":"additional","affiliation":[]},{"given":"Chick","family":"Markley","sequence":"additional","affiliation":[]},{"given":"Jim","family":"Lawson","sequence":"additional","affiliation":[]},{"given":"Jonathan","family":"Bachrach","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","year":"0","journal-title":"CoreMark An EEMBC Benchmark"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2872362.2872414"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228584"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/92.820756"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707895"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228472"},{"key":"ref37","article-title":"The Rocket Chip Generator","author":"asanovi?","year":"2016","journal-title":"EECS Department University of California Berkeley Tech Rep UCB\/EECS-2009-28"},{"key":"ref36","article-title":"Specification for the FIR-RTL Language","author":"li","year":"2016","journal-title":"EECS Department University of California Berkeley Tech Rep UCB\/EECS-2009-28"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/CGO.2004.1281665"},{"key":"ref34","article-title":"An overview of the Scala programming language","author":"odersky","year":"2004","journal-title":"Tech Rep"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950423"},{"key":"ref40","article-title":"The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor","author":"celio","year":"2015","journal-title":"EECS Department University of California Berkeley Tech Rep UCB\/EECS-2009-28"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2007.107"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339272"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/FCCM.2011.19"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/SASP.2009.5226333"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/1869459.1869469"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2014.6927454"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-78610-8_30"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2159542.2159547"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1145\/1450095.1450105"},{"key":"ref28","author":"takamaeda-yamazaki","year":"0","journal-title":"Veriloggen A library for constructing a Verilog HDL source code in Python"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2010.81"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-16214-0_5"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2011.18"},{"key":"ref6","article-title":"Synthesizing systemverilog: Busting the myth that systemverilog is only for verification","author":"sutherland","year":"2013","journal-title":"Silicon Valley"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2014.50"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TVCG.2011.185"},{"key":"ref8","year":"0","journal-title":"Catapult and PowerPro High-Level Synthesis and RTL Low-Power"},{"key":"ref7","year":"0","journal-title":"Vivado High-Level Synthesis"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1815961.1815968"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4020-8588-8_9"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736044"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/MEMCOD.2004.1459818"},{"key":"ref22","author":"wolf","year":"0","journal-title":"Yosys Open SYnthesis Suite"},{"key":"ref21","first-page":"1","article-title":"IEEE Standard for Standard SystemC Language Reference Manual","year":"2012","journal-title":"IEEE Std 1666–2011 (Revision of IEEE Std 1666–2005)"},{"key":"ref42","year":"0","journal-title":"ChipScope Pro Debugging Overview"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-16214-0_42"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/MSE.2009.5270840"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.1999.781371"},{"key":"ref26","first-page":"5","article-title":"MyHDL: A Python-based Hardware Description Language","volume":"2004","author":"decaluwe","year":"2004","journal-title":"Linux J"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2016.21"},{"key":"ref25","year":"0","journal-title":"Verific Design Automation"}],"event":{"name":"2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","location":"Irvine, CA","start":{"date-parts":[[2017,11,13]]},"end":{"date-parts":[[2017,11,16]]}},"container-title":["2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8167715\/8203744\/08203780.pdf?arnumber=8203780","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,1,22]],"date-time":"2018-01-22T17:33:08Z","timestamp":1516642388000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8203780\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":43,"URL":"https:\/\/doi.org\/10.1109\/iccad.2017.8203780","relation":{},"subject":[],"published":{"date-parts":[[2017,11]]}}}