{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,5]],"date-time":"2026-06-05T15:54:39Z","timestamp":1780674879409,"version":"3.54.1"},"reference-count":33,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/iccad.2017.8203799","type":"proceedings-article","created":{"date-parts":[[2017,12,14]],"date-time":"2017-12-14T17:02:04Z","timestamp":1513270924000},"page":"352-359","source":"Crossref","is-referenced-by-count":16,"title":["Enabling exact delay synthesis"],"prefix":"10.1109","author":[{"given":"Luca","family":"Amaru","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mathias","family":"Soeken","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Patrick","family":"Vuillod","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiong","family":"Luo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Alan","family":"Mishchenko","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Janet","family":"Olson","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Robert","family":"Brayton","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref33","year":"0"},{"key":"ref32","article-title":"SAT-based optimization with don't-cares revisited","author":"mishchenko","year":"0","journal-title":"IWLS&#x2019; 17"},{"key":"ref31","article-title":"SAT-based area recovery in technology mapping","author":"schmitt","year":"0","journal-title":"IWLS'17"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2017.7927194"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/996566.996691"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/2593069.2593227"},{"key":"ref12","article-title":"The EPFL Combinational Benchmark Suite","author":"amaru","year":"2015","journal-title":"Int Workshop on Logic Synthesis (IWLS)"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2017.7858313"},{"key":"ref14","author":"ernst","year":"2009","journal-title":"Optimal combinational multi-level logic synthesis"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/FOCS.1961.1"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1147\/rd.62.0227"},{"key":"ref17","volume":"4a","author":"knuth","year":"0","journal-title":"The art of computer programming"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1972.5009010"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-02777-2_5"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/PGEC.1963.263656"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/5.52213"},{"key":"ref27","article-title":"Classifying n-input Boolean functions","author":"correia","year":"2001","journal-title":"Proc IWLS"},{"key":"ref3","first-page":"597604","article-title":"Lazy mans logic synthesis","author":"yang","year":"2012","journal-title":"ICCAD"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/605440.605442"},{"key":"ref29","year":"0","journal-title":"Abc Synthesis Tools"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1990.112064"},{"key":"ref8","author":"de micheli","year":"1994","journal-title":"Synthesis and Optimization of Digital Circuits"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2488484"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105357"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1997.643371"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1137\/0403021"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/T-C.1969.222593"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2664059"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675229"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147048"},{"key":"ref23","article-title":"Busy Mans Synthesis: Combinational Delay Optimization With SAT","author":"soeken","year":"2017","journal-title":"Proc of the Conference on Design Automation and Test in Europe (DATE)"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref25","author":"hassoun","year":"2001","journal-title":"Logic Synthesis and Verification"}],"event":{"name":"2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","location":"Irvine, CA","start":{"date-parts":[[2017,11,13]]},"end":{"date-parts":[[2017,11,16]]}},"container-title":["2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8167715\/8203744\/08203799.pdf?arnumber=8203799","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,1,22]],"date-time":"2018-01-22T17:33:34Z","timestamp":1516642414000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8203799\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":33,"URL":"https:\/\/doi.org\/10.1109\/iccad.2017.8203799","relation":{},"subject":[],"published":{"date-parts":[[2017,11]]}}}