{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,11]],"date-time":"2026-04-11T00:47:41Z","timestamp":1775868461961,"version":"3.50.1"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,11]]},"DOI":"10.1109\/iccad.2017.8203809","type":"proceedings-article","created":{"date-parts":[[2017,12,14]],"date-time":"2017-12-14T17:02:04Z","timestamp":1513270924000},"page":"430-437","source":"Crossref","is-referenced-by-count":93,"title":["COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications"],"prefix":"10.1109","author":[{"given":"Jieru","family":"Zhao","sequence":"first","affiliation":[]},{"given":"Liang","family":"Feng","sequence":"additional","affiliation":[]},{"given":"Sharad","family":"Sinha","sequence":"additional","affiliation":[]},{"given":"Wei","family":"Zhang","sequence":"additional","affiliation":[]},{"given":"Yun","family":"Liang","sequence":"additional","affiliation":[]},{"given":"Bingsheng","family":"He","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2014.6853195"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/192724.192731"},{"key":"ref12","first-page":"97","article-title":"Aladdin:a pre-rtl, power-performance accelerator simulator enabling large design space exploration of customized architectures","author":"shao","year":"2014","journal-title":"Proc of ISCA"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2660769"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1145\/3061639.3062251"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446058"},{"key":"ref16","year":"0","journal-title":"Xilinx"},{"key":"ref17","year":"0","journal-title":"Xilinx Vivado design suite user guide high-level synthesis v2016 1"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/2684746.2689060"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2014.6974719"},{"key":"ref4","first-page":"506","article-title":"Dynamic critical-path scheduling: An effective technique for allocating task graphs to multiprocessors","volume":"7","author":"kwok","year":"1996","journal-title":"TPDS"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.2197\/ipsjjip.17.242"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"200","DOI":"10.1145\/2684746.2689065","article-title":"Resource-aware throughput optimization for high-level synthesis","author":"li","year":"2015","journal-title":"Proc of FPGA"},{"key":"ref5","author":"lattner","year":"2005","journal-title":"An Implementation of Swing Modulo Scheduling with Extensions for Superblocks"},{"key":"ref8","first-page":"157","article-title":"Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis","author":"pham","year":"2015","journal-title":"2012 Design Automation & Test in Europe Conference & Exhibition (DATE) DATE"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2463209.2488795"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"234","DOI":"10.1145\/2847263.2847282","article-title":"Automatically optimizing the latency, area, and accuracy of c programs for high-level synthesis","author":"gao","year":"2016","journal-title":"Proc of FPGA"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.141"},{"key":"ref9","author":"pouchet","year":"0","journal-title":"PolyBench\/C 4 2"},{"key":"ref20","first-page":"136","article-title":"Lin-analyzer: a high-level performance analysis tool for fpga-based accelerators","author":"zhong","year":"2016","journal-title":"Proc of DAC"}],"event":{"name":"2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","location":"Irvine, CA","start":{"date-parts":[[2017,11,13]]},"end":{"date-parts":[[2017,11,16]]}},"container-title":["2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8167715\/8203744\/08203809.pdf?arnumber=8203809","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,25]],"date-time":"2022-01-25T18:02:33Z","timestamp":1643133753000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/8203809\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,11]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/iccad.2017.8203809","relation":{},"subject":[],"published":{"date-parts":[[2017,11]]}}}