{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T14:54:53Z","timestamp":1777128893076,"version":"3.51.4"},"reference-count":48,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,11,1]],"date-time":"2019-11-01T00:00:00Z","timestamp":1572566400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,11]]},"DOI":"10.1109\/iccad45719.2019.8942112","type":"proceedings-article","created":{"date-parts":[[2020,1,3]],"date-time":"2020-01-03T00:44:25Z","timestamp":1578012265000},"page":"1-7","source":"Crossref","is-referenced-by-count":13,"title":["SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks"],"prefix":"10.1109","author":[{"given":"Darshana","family":"Jayasinghe","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Aleksandar","family":"Ignjatovic","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sri","family":"Parameswaran","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"Scrip repository"},{"key":"ref2","year":"2001","journal-title":"Federal Information Processing Standards Publication 197 announcing the advanced encryption standard (aes)"},{"key":"ref3","volume-title":"Lowrisc version 0.2 fpga demo","year":"2015"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-36400-5_4"},{"key":"ref5","volume-title":"Altera i\/o phase-locked loop (altera iopll) ip core","year":"2015"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2009.0097"},{"key":"ref7","first-page":"489","author":"Ambrose","year":"2007","journal-title":"Rijid: Random code injection to mask power analysis based side channel attacks"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2013.6654626"},{"key":"ref9","volume-title":"The rocket chip generator","author":"Asanovi\u00c4\u011e","year":"2016"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2007.79"},{"key":"ref11","volume-title":"Cache-timing attacks on aes","author":"Bernstein","year":"2005"},{"key":"ref12","volume-title":"Nicv: Normalized inter-class variance for detection of side-channel leakage","author":"Bhasin","year":"2013"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-45126-6_12"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-28632-5_2"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-662-45608-8_19"},{"key":"ref16","volume-title":"Busybox: The swiss army knife of embedded linux","year":"2019"},{"key":"ref17","article-title":"Test vector leakage assessment (tvla) methodology in practice","volume-title":"ICMC 2013","author":"Cooper","year":"2013"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-15031-9_7"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/SP.2017.58"},{"key":"ref20","volume-title":"Memory deep dive: Memory subsystem bandwidth","author":"Denneman","year":"2015"},{"key":"ref21","first-page":"123","volume-title":"Efficient Removal of Random Delays from Embedded Software Implementations Using Hidden Markov Models","author":"Durvaux","year":"2013"},{"key":"ref22","volume-title":"How to protect risc-v against side-channel attacks?","author":"De Mulder","year":"2018"},{"key":"ref23","first-page":"193","article-title":"Sliding-window correlation attacks against encryption devices with an unstable clock","volume-title":"Selected Areas in Cryptography - SAC 2018\u201325th International Conference","author":"Fledel"},{"key":"ref24","volume-title":"Risc-v cores","year":"2019"},{"key":"ref25","first-page":"89","article-title":"Concealing secrets in embedded processors designs","volume-title":"Smart Card Research and Advanced Applications - 15th International Conference, CARDIS 2016","author":"Gro\u00df"},{"key":"ref26","volume-title":"Principal component analysis and side-channel attacks","author":"Hogenboom","year":"2010"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/GCCE.2012.6379944"},{"key":"ref28","first-page":"104","volume-title":"Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems","author":"Kocher","year":"1996"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"ref30","volume-title":"Lowrisc code repository","year":"2015"},{"key":"ref31","volume-title":"Lowrisc version 0.2","year":"2015"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2012.6339236"},{"key":"ref33","volume-title":"Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)","author":"Mangard","year":"2007"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2012.6176671"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_6"},{"key":"ref36","article-title":"A generic countermeasure against fault injection attacks on asymmetric cryptography","volume-title":"IACR Cryptology ePrint Archive","volume":"882","author":"Rauzy","year":"2015"},{"key":"ref37","volume-title":"Leon processors","year":"2019"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1007\/11894063_21"},{"key":"ref39","volume-title":"Mmcm and pll dynamic reconfiguration","author":"Tatsukawa","year":"2017"},{"key":"ref40","first-page":"354","volume-title":"Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment","author":"Tiri","year":"2005"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-19074-2_8"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.2307\/2332510"},{"key":"ref43","volume-title":"7 series fpgas clocking resources","year":"2011"},{"key":"ref44","volume-title":"Cost-optimized portfolio product tables and product selection guide","year":"2015"},{"key":"ref45","volume-title":"Xilinx ultrascale plus product guide","year":"2015"},{"key":"ref46","volume-title":"Axi interconnect v2.1-pg059","year":"2017"},{"key":"ref47","volume-title":"Microblaze soft processor core","year":"2019"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.887921"}],"event":{"name":"2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)","location":"Westminster, CO, USA","start":{"date-parts":[[2019,11,4]]},"end":{"date-parts":[[2019,11,7]]}},"container-title":["2019 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8931666\/8942037\/08942112.pdf?arnumber=8942112","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,23]],"date-time":"2024-01-23T23:51:21Z","timestamp":1706053881000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8942112\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,11]]},"references-count":48,"URL":"https:\/\/doi.org\/10.1109\/iccad45719.2019.8942112","relation":{},"subject":[],"published":{"date-parts":[[2019,11]]}}}