{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,19]],"date-time":"2026-06-19T15:48:37Z","timestamp":1781884117202,"version":"3.54.5"},"reference-count":25,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,10,28]],"date-time":"2023-10-28T00:00:00Z","timestamp":1698451200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,10,28]],"date-time":"2023-10-28T00:00:00Z","timestamp":1698451200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62090025,62141407,61929102"],"award-info":[{"award-number":["62090025,62141407,61929102"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,10,28]]},"DOI":"10.1109\/iccad57390.2023.10323694","type":"proceedings-article","created":{"date-parts":[[2023,11,30]],"date-time":"2023-11-30T18:58:45Z","timestamp":1701370725000},"page":"1-9","source":"Crossref","is-referenced-by-count":4,"title":["Sphinx: A Hybrid Boolean Processor-FPGA Hardware Emulation System"],"prefix":"10.1109","author":[{"given":"Ruiyao","family":"Pu","sequence":"first","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yiwei","family":"Sun","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Pei-Hsin","family":"Ho","sequence":"additional","affiliation":[{"name":"UniVista Industrial Software Group,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Fan","family":"Yang","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Li","family":"Shang","sequence":"additional","affiliation":[{"name":"School of Computer Science, Fudan University,China and Shanghai Key Laboratory of Data Science,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Xuan","family":"Zeng","sequence":"additional","affiliation":[{"name":"School of Microelectronics, Fudan University,State Key Lab of Integrated Chips and Systems,Shanghai,China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1201\/9781420007947"},{"key":"ref2","article-title":"Cadence Palladium","volume-title":"Cadence","year":"2022"},{"key":"ref3","article-title":"Synopsys ZeBu","volume-title":"Synopsys","year":"2022"},{"key":"ref4","article-title":"Mentor Veloce","volume-title":"Mentor Graphics","year":"2022"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IWRSP.2000.855197"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1080\/00207217.2010.512017"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1950413.1950438"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DDECS.2016.7482447"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC.2002.1012690"},{"key":"ref10","author":"Yazdanshenas","year":"2006","journal-title":"Hardware design and cad for processor-based logic emulation systems"},{"key":"ref11","author":"Kanaan","year":"2007","journal-title":"A low-cost processor-based logic emulation system using fpgas"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1145\/3543622.3573187"},{"key":"ref13","volume-title":"Yosys Open Synthesis Suite","author":"Wolf","year":"2013"},{"key":"ref14","article-title":"COEfficient","volume-title":"AMD","year":"2022"},{"key":"ref15","article-title":"Vivado","volume-title":"XILINX"},{"key":"ref16","article-title":"FPGA Bitstream","volume-title":"XILINX"},{"key":"ref17","article-title":"Multiprocessor for hardware emulation","author":"Beausoleil","year":"1994","journal-title":"U.S. Patent 5551013"},{"key":"ref18","volume-title":"METIS","author":"Karypis"},{"key":"ref19","volume-title":"biRISC-V - 32-bit dual issue RISC-V CPU"},{"key":"ref20","volume-title":"DES-Encryption"},{"key":"ref21","volume-title":"AES-FPGA"},{"key":"ref22","volume-title":"SHA256-Accelerator-Hardware"},{"key":"ref23","article-title":"Chipscope Pro Software and Cores: User Guide","volume-title":"XILINX"},{"key":"ref24","article-title":"Integrated Logic Analyzer v6.2","volume-title":"XILINX"},{"key":"ref25","article-title":"Incremental Implementation","volume-title":"XILINX"}],"event":{"name":"2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD)","location":"San Francisco, CA, USA","start":{"date-parts":[[2023,10,28]]},"end":{"date-parts":[[2023,11,2]]}},"container-title":["2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10323590\/10323543\/10323694.pdf?arnumber=10323694","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T22:04:16Z","timestamp":1709417056000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10323694\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10,28]]},"references-count":25,"URL":"https:\/\/doi.org\/10.1109\/iccad57390.2023.10323694","relation":{},"subject":[],"published":{"date-parts":[[2023,10,28]]}}}