{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,2]],"date-time":"2026-01-02T07:29:20Z","timestamp":1767338960725,"version":"3.37.3"},"reference-count":32,"publisher":"IEEE","license":[{"start":{"date-parts":[[2023,10,28]],"date-time":"2023-10-28T00:00:00Z","timestamp":1698451200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,10,28]],"date-time":"2023-10-28T00:00:00Z","timestamp":1698451200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key R&D Program of China","doi-asserted-by":"publisher","award":["2022YFB4501703"],"award-info":[{"award-number":["2022YFB4501703"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2023,10,28]]},"DOI":"10.1109\/iccad57390.2023.10323959","type":"proceedings-article","created":{"date-parts":[[2023,11,30]],"date-time":"2023-11-30T18:58:45Z","timestamp":1701370725000},"page":"1-9","source":"Crossref","is-referenced-by-count":1,"title":["Fast and Scalable Gate-Level Simulation in Massively Parallel Systems"],"prefix":"10.1109","author":[{"given":"Haichuan","family":"Hu","sequence":"first","affiliation":[{"name":"National Engineering Research Center for Big Data Technology and System, School of Computer Science and Technology, Huazhong University of Science and Technology,Services Computing Technology and System Lab, Cluster and Grid Computing Lab,Wuhan,China,430074"}]},{"given":"Zichen","family":"Xu","sequence":"additional","affiliation":[{"name":"School of Mathematics and Computer Science, Nanchang University,Nanchang,China"}]},{"given":"Yuhao","family":"Wang","sequence":"additional","affiliation":[{"name":"School of Mathematics and Computer Science, Nanchang University,Nanchang,China"}]},{"given":"Fangming","family":"Liu","sequence":"additional","affiliation":[{"name":"National Engineering Research Center for Big Data Technology and System, School of Computer Science and Technology, Huazhong University of Science and Technology,Services Computing Technology and System Lab, Cluster and Grid Computing Lab,Wuhan,China,430074"}]}],"member":"263","reference":[{"issue":"99","key":"ref1","first-page":"3","article-title":"Icarus verilog: open-source verilog more than a year later","volume":"2002","author":"Williams","year":"2002","journal-title":"Linux Journal"},{"key":"ref2","article-title":"Bucknell handbook on verilog hdl","author":"Hyde","year":"1995","journal-title":"Com puter Science Department, Bucknell University Lewis burg"},{"key":"ref3","first-page":"35","article-title":"Cadence design environment","author":"Martin","year":"2002","journal-title":"New Mexico State University, Tutorial paper"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2954679.2872414"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/978-90-481-9591-6"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.21236\/ada447721"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1063\/1.5030730"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/DS-RT.2016.31"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3013528"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3064911.3064912"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-64182-9_7"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICPR.2006.463"},{"key":"ref13","article-title":"Iwls 2005 benchmarks","volume-title":"International Workshop for Logic Synthesis (IWLS)","author":"Albrecht","year":"2005"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2821924"},{"key":"ref15","first-page":"7364","article-title":"Circuit-gnn: Graph neural networks for distributed circuit design","volume-title":"International conference on machine learning","author":"Zhang","year":"2019"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2019.2907922"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2017.2754192"},{"key":"ref18","first-page":"269","article-title":"Controlling memory footprint of stateful streaming graph processing","volume-title":"USENIX Annual Technical Conference","author":"Vaziri","year":"2021"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1155\/2014\/529392"},{"key":"ref20","article-title":"The epfl combinational benchmark suite","volume-title":"Proceedings of the 24th International Workshop on Logic & Synthesis (IWLS)","author":"Amar\u00fa","year":"2015"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2825362"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/1143997.1144099"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1145\/2513109.2513110"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580063"},{"issue":"1","key":"ref25","article-title":"Hyper-threading technology architecture and microarchitecture","volume":"6","author":"Marr","year":"2002","journal-title":"Intel Technology Journal"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30218-6_19"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643481"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3316781.3317878","article-title":"Partition and propagate: An error derivation algorithm for the design of approximate circuits","volume-title":"Proceedings of the 56th Annual Design Automation Conference 2019","author":"Scarabottolo","year":"2019"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2021.3139310"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643571"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ITC-Asia51099.2020.00032"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3437959.3459249"}],"event":{"name":"2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD)","start":{"date-parts":[[2023,10,28]]},"location":"San Francisco, CA, USA","end":{"date-parts":[[2023,11,2]]}},"container-title":["2023 IEEE\/ACM International Conference on Computer Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10323590\/10323543\/10323959.pdf?arnumber=10323959","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,2]],"date-time":"2024-03-02T22:18:27Z","timestamp":1709417907000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10323959\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10,28]]},"references-count":32,"URL":"https:\/\/doi.org\/10.1109\/iccad57390.2023.10323959","relation":{},"subject":[],"published":{"date-parts":[[2023,10,28]]}}}