{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T05:51:31Z","timestamp":1763704291479,"version":"3.45.0"},"reference-count":29,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T00:00:00Z","timestamp":1761436800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T00:00:00Z","timestamp":1761436800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,10,26]]},"DOI":"10.1109\/iccad66269.2025.11240698","type":"proceedings-article","created":{"date-parts":[[2025,11,20]],"date-time":"2025-11-20T18:39:34Z","timestamp":1763663974000},"page":"1-9","source":"Crossref","is-referenced-by-count":0,"title":["ExactMap: Enhancing Delay Optimization in Parallel ASIC Technology Mapping"],"prefix":"10.1109","author":[{"given":"Zhenxuan","family":"Xie","sequence":"first","affiliation":[{"name":"The Chinese University of Hong Kong,Department of Computer Science &amp; Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Lixin","family":"Liu","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong,Department of Computer Science &amp; Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tianji","family":"Liu","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong,Department of Computer Science &amp; Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Evangeline F.Y.","family":"Young","sequence":"additional","affiliation":[{"name":"The Chinese University of Hong Kong,Department of Computer Science &amp; Engineering"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-642-14295-6_5"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247905"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323999"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3658617.3697722"},{"key":"ref5","first-page":"209","article-title":"On the complexity of minimum-delay gate resizing\/technology mapping under load-dependent delay model","volume-title":"Workshop Handouts, International Workshop on Logic Synthesis","author":"Murgai"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3457378"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/37888.37940"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2007.4397290"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586230"},{"key":"ref10","first-page":"1","article-title":"Leap: Learning guided quality cut selection for faster technology mapping","volume-title":"Proceedings of the 43rd IEEE\/ACM International Conference on Computer-Aided Design","author":"Chigarapally"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD58817.2023.00059"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3524463"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1145\/3676536.3676762","article-title":"Maptune: Advancing asic technology mapping via reinforcement learning guided library tuning","author":"Liu","year":"2024"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473941"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3655987"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530485"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676787"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676651"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2022.3217668"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/54.785838"},{"article-title":"The epfl combinational benchmark suite","volume-title":"Proceedings of the 24th International Workshop on Logic & Synthesis (IWLS)","author":"Amar\u00fa","key":"ref21"},{"key":"ref22","article-title":"Iwls 2005 benchmarks","volume-title":"International Workshop for Logic Synthesis (IWLS)","volume":"9","author":"Albrecht"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2016.04.006"},{"year":"2008","key":"ref24","article-title":"Nangate 45nm open cell library"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882484"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.882119"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530462"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247961"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3429079"}],"event":{"name":"2025 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)","start":{"date-parts":[[2025,10,26]]},"location":"Munich, Germany","end":{"date-parts":[[2025,10,30]]}},"container-title":["2025 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11240608\/11240621\/11240698.pdf?arnumber=11240698","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T05:43:09Z","timestamp":1763703789000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11240698\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,26]]},"references-count":29,"URL":"https:\/\/doi.org\/10.1109\/iccad66269.2025.11240698","relation":{},"subject":[],"published":{"date-parts":[[2025,10,26]]}}}