{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,15]],"date-time":"2025-12-15T14:21:50Z","timestamp":1765808510573,"version":"3.45.0"},"reference-count":50,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T00:00:00Z","timestamp":1761436800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T00:00:00Z","timestamp":1761436800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,10,26]]},"DOI":"10.1109\/iccad66269.2025.11240762","type":"proceedings-article","created":{"date-parts":[[2025,11,20]],"date-time":"2025-11-20T18:39:34Z","timestamp":1763663974000},"page":"1-9","source":"Crossref","is-referenced-by-count":1,"title":["GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment"],"prefix":"10.1109","author":[{"given":"Wenji","family":"Fang","sequence":"first","affiliation":[{"name":"Hong Kong University of Science and Technology"}]},{"given":"Wang","family":"Jing","sequence":"additional","affiliation":[{"name":"Hong Kong University of Science and Technology"}]},{"given":"Yao","family":"Lu","sequence":"additional","affiliation":[{"name":"Hong Kong University of Science and Technology"}]},{"given":"Shang","family":"Liu","sequence":"additional","affiliation":[{"name":"Hong Kong University of Science and Technology"}]},{"given":"Zhiyao","family":"Xie","sequence":"additional","affiliation":[{"name":"Hong Kong University of Science and Technology"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/s11432-024-4155-7"},{"article-title":"A survey of circuit foundation model: Foundation ai models for vlsi circuit design and eda","year":"2025","author":"Fang","key":"ref2"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/3658617.3697597"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676791"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD57390.2023.10323798"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530497"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3489517.3530410"},{"article-title":"Circuitfusion: multimodal circuit representation learning for agile chip design","volume-title":"International Conference on Learning Representations (ICLR)","author":"Fang","key":"ref8"},{"article-title":"Circuit representationlearning with masked gatemodeling and verilog-aigalignment","volume-title":"International Conference on Learning Representations (ICLR)","author":"Wu","key":"ref9"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3657386"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1145\/3613424.3623794","article-title":"Fast, robust and transferable prediction for hardware logic synthesis","volume-title":"IEEE\/ACM International Symposium on Microarchitecture (MICRO)","author":"Xu"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/LAD62341.2024.10691738"},{"article-title":"Betterv: Controlled verilog generation with discriminative guidance","year":"2024","author":"Pei","key":"ref13"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/LAD62341.2024.10691788"},{"key":"ref15","article-title":"AssertLLM: Generating and evaluating hardware verification assertions from design specifications via multi-LLMs","author":"Yan","year":"2025","journal-title":"ASP-DAC"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TIFS.2024.3372809"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MLCAD58807.2023.10299852"},{"article-title":"Deepgate4: Efficient and effective representation learning for circuit design at scale","volume-title":"International Conference on Learning Representations (ICLR)","author":"Zheng","key":"ref18"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DAC63849.2025.11133349"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2024.3483089"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3735638"},{"article-title":"DeepRTL: Bridging verilog understanding and generation with a unified representation model","volume-title":"International Conference on Learning Representations (ICLR)","author":"Liu","key":"ref22"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DAC56929.2023.10247828"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2024.3434464"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804386"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.7873\/DATE.2013.264"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1145\/3658617.3697594"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676834"},{"article-title":"Chip-NeMo: Domain-Adapted LLMs for Chip Design","year":"2023","author":"Liu","key":"ref29"},{"article-title":"Chipgpt: How far are we from natural language hardware design","year":"2023","author":"Chang","key":"ref30"},{"article-title":"Towards improving verification productivity with circuit-aware translation of natural language to systemverilog assertions","volume-title":"International Workshop on Deep Learning-aided Verification (DAV)","author":"Sun","key":"ref31"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676775"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/3676536.3676750"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2024.3383347"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2012.6224325"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/FMCAD.2014.6987599"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/tcad.2021.3110807"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643498"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC58780.2024.10473904"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/iccad57390.2023.10323812"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/54.867894"},{"volume-title":"OpenCores: The reference community for Free and Open Source gate-ware IP cores","key":"ref42"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2996616"},{"year":"2022","key":"ref44","article-title":"VexRiscv: A FPGA friendly 32 bit RISC-V CPU implementation"},{"article-title":"Yosys-a free verilog synthesis suite","volume-title":"Austrian Workshop on Microelectronics (Austrochip)","author":"Wolf","key":"ref45"},{"article-title":"Deepseek-coder: When the large language model meets programming\u2013the rise of code intelligence","year":"2024","author":"Guo","key":"ref46"},{"article-title":"Deepseek-v3 technical report","year":"2024","author":"Liu","key":"ref47"},{"key":"ref48","article-title":"Visual instruction tuning","volume":"36","author":"Liu","year":"2024","journal-title":"Advances in neural information processing systems"},{"article-title":"Blip-2: Bootstrapping language-image pre-training with frozen image encoders and large language models","volume-title":"ICML","author":"Li","key":"ref49"},{"article-title":"Blip: Bootstrapping language-image pre-training for unified vision-language understanding and generation","volume-title":"International Conference on Machine Learning (ICML)","author":"Li","key":"ref50"}],"event":{"name":"2025 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)","start":{"date-parts":[[2025,10,26]]},"location":"Munich, Germany","end":{"date-parts":[[2025,10,30]]}},"container-title":["2025 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11240608\/11240621\/11240762.pdf?arnumber=11240762","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T05:44:02Z","timestamp":1763703842000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11240762\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,26]]},"references-count":50,"URL":"https:\/\/doi.org\/10.1109\/iccad66269.2025.11240762","relation":{},"subject":[],"published":{"date-parts":[[2025,10,26]]}}}