{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,10]],"date-time":"2026-07-10T16:23:50Z","timestamp":1783700630166,"version":"3.55.0"},"reference-count":23,"publisher":"IEEE","license":[{"start":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T00:00:00Z","timestamp":1761436800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,10,26]],"date-time":"2025-10-26T00:00:00Z","timestamp":1761436800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2025,10,26]]},"DOI":"10.1109\/iccad66269.2025.11240782","type":"proceedings-article","created":{"date-parts":[[2025,11,20]],"date-time":"2025-11-20T18:39:34Z","timestamp":1763663974000},"page":"1-9","source":"Crossref","is-referenced-by-count":1,"title":["PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation"],"prefix":"10.1109","author":[{"given":"Raghul","family":"Saravanan","sequence":"first","affiliation":[{"name":"George Mason University,Dept. of ECE,Fairfax,VA,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sudipta","family":"Paria","sequence":"additional","affiliation":[{"name":"University of Florida,Dept. of ECE,Gainesville,FL,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Aritra","family":"Dasgupta","sequence":"additional","affiliation":[{"name":"University of Florida,Dept. of ECE,Gainesville,FL,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Swarup","family":"Bhunia","sequence":"additional","affiliation":[{"name":"University of Florida,Dept. of ECE,Gainesville,FL,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Sai Manoj","family":"P D","sequence":"additional","affiliation":[{"name":"George Mason University,Dept. of ECE,Fairfax,VA,USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.49"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2015.107"},{"key":"ref3","article-title":"Hardfails: Insights into software-exploitable hardware bugs","volume-title":"USENIX Conference on Security Symposium","author":"Dessouky"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.41"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364684"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240842"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS51556.2021.9401267"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/SP40001.2021.00103"},{"key":"ref9","article-title":"Fuzzing hardware like software","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Trippel"},{"key":"ref10","doi-asserted-by":"crossref","DOI":"10.1145\/3400302.3415709","article-title":"Hyperfuzzing for SoC security validation","volume-title":"IEEE\/ACM International Conference On Computer Aided Design (ICCAD)","author":"Muduli"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/3466752.3480092"},{"key":"ref12","article-title":"TheHuzz: Instruction fuzzing of processors using Golden-Reference models for finding Software-Exploitable vulnerabilities","volume-title":"USENIX Security Symposium (USENIX Security)","author":"Kande"},{"key":"ref13","article-title":"Microsoft security risk detection"},{"key":"ref14","first-page":"1361","article-title":"HyPFuzz: Formal-Assisted processor fuzzing","author":"Chen","year":"2023"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/HOST55118.2023.10133714"},{"key":"ref16","article-title":"Risc-v"},{"key":"ref17","article-title":"mor1kx - an openrisc processor IP core"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DAC18074.2021.9586289"},{"key":"ref19","article-title":"Americal fuzzy loop"},{"key":"ref20","article-title":"Welcome to verilator"},{"key":"ref21","article-title":"VCS: The industry\u2019s highest performance simulation solutions"},{"key":"ref22","article-title":"Fastest simulator to achieve verification closure for IP and SoC designs"},{"key":"ref23","article-title":"Cadence webpage"}],"event":{"name":"2025 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)","location":"Munich, Germany","start":{"date-parts":[[2025,10,26]]},"end":{"date-parts":[[2025,10,30]]}},"container-title":["2025 IEEE\/ACM International Conference On Computer Aided Design (ICCAD)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11240608\/11240621\/11240782.pdf?arnumber=11240782","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,21]],"date-time":"2025-11-21T05:44:16Z","timestamp":1763703856000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11240782\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,10,26]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/iccad66269.2025.11240782","relation":{},"subject":[],"published":{"date-parts":[[2025,10,26]]}}}