{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T06:17:11Z","timestamp":1725603431515},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,7]]},"DOI":"10.1109\/icccnt.2018.8494059","type":"proceedings-article","created":{"date-parts":[[2018,12,7]],"date-time":"2018-12-07T21:34:56Z","timestamp":1544218496000},"page":"1-3","source":"Crossref","is-referenced-by-count":2,"title":["LVCMOS Based 4-Bit Register"],"prefix":"10.1109","author":[{"given":"Tarun","family":"Agrawal","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anjan","family":"Kumar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Priyanka","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pooja","family":"Aggarwal","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Syed Saad","family":"Tirmizi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICSSS.2014.7006182"},{"key":"ref3","article-title":"An Efficient Design of 4-Bit Serial Input Parallel Output\/Serial Output Shift Register in Quantum Dot Cellular Automata","author":"padmnabhan","year":"2016","journal-title":"International Conference of IEEE"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.14445\/22312803\/IJCTT-V50P118"},{"key":"ref6","doi-asserted-by":"crossref","DOI":"10.1515\/9783110450101","article-title":"Designing of Random Access Memory Using Different IO Standard Technology","author":"kumar","year":"2016","journal-title":"7th International Conference on Computing Communication and Networking Technologies"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/CCIntelS.2016.7878231"},{"journal-title":"8T based SRAM cell and related method","year":"2013","author":"kushwah","key":"ref8"},{"key":"ref7","article-title":"Designing of Power Efficient ROM Using LVTTL and Mobile-DDR IO Standard on 28nm FPGA","author":"kumar","year":"2015","journal-title":"IEEE International Conference on Computational Intelligence and Communication Networks"},{"key":"ref2","article-title":"Implementation of Configurable Linear FeedbackShift Register in VHDL","author":"mishra","year":"2016","journal-title":"International Conference on Emerging Trends in Electrical Electronics and Sustainable Energy Systems"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IICPE.2014.7115800"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/77.622208"}],"event":{"name":"2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT)","start":{"date-parts":[[2018,7,10]]},"location":"Bangalore","end":{"date-parts":[[2018,7,12]]}},"container-title":["2018 9th International Conference on Computing, Communication and Networking Technologies (ICCCNT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8476666\/8493493\/08494059.pdf?arnumber=8494059","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,24]],"date-time":"2020-08-24T05:21:50Z","timestamp":1598246510000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8494059\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/icccnt.2018.8494059","relation":{},"subject":[],"published":{"date-parts":[[2018,7]]}}}