{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,11,28]],"date-time":"2024-11-28T05:13:57Z","timestamp":1732770837019,"version":"3.29.0"},"reference-count":24,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,6,24]],"date-time":"2024-06-24T00:00:00Z","timestamp":1719187200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,6,24]],"date-time":"2024-06-24T00:00:00Z","timestamp":1719187200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,6,24]]},"DOI":"10.1109\/icccnt61001.2024.10723922","type":"proceedings-article","created":{"date-parts":[[2024,11,4]],"date-time":"2024-11-04T23:06:46Z","timestamp":1730761606000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["FPGA Implementation of XOR-MUX based Full Adder and Truncated Multiplier for Signal Processing Applications"],"prefix":"10.1109","author":[{"given":"P","family":"Pavithara","sequence":"first","affiliation":[{"name":"Kongu Engineering College, Perundurai,Department of Electronics and Communication Engineering,Erode,638060"}]},{"given":"N R","family":"Raghapriya","sequence":"additional","affiliation":[{"name":"Erode Sengunthar Engineering College,Department of Computer Science and Engineering,Thuduppathi,638057"}]},{"given":"P M","family":"Dinesh","sequence":"additional","affiliation":[{"name":"Sona College of Technology,Department of Electronics and Communication Engineering,Salem,636005"}]},{"given":"S","family":"Gowtham","sequence":"additional","affiliation":[{"name":"KSR College of Engineering,Department of Electrical and Electronics Engineering,Tiruchengode,637215"}]},{"given":"D","family":"Viji","sequence":"additional","affiliation":[{"name":"Erode Sengunthar Engineering College,Department of Artificial Intelligence and Data Science,Thuduppathi,638057"}]},{"given":"K","family":"Kavin Kumar","sequence":"additional","affiliation":[{"name":"Kongu Engineering College, Perundurai,Department of Electronics and Communication Engineering,Erode,638060"}]},{"given":"Gokul","family":"Chandrasekaran","sequence":"additional","affiliation":[{"name":"Karpagam Institute of Technology,Department of Electronics and Communication Engineering,Coimbatore"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/RAICS.2015.7488381"},{"key":"ref2","article-title":"High Speed Gate Level Synchronous Full Adder Designs","author":"Balasubramani","year":"2015","journal-title":"WSEAS Transactions on Circuits and Systems"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ICoCS.2014.7060929"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3400302.3415700"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-020-01559-8"},{"key":"ref6","first-page":"3796","article-title":"Design of adder\/subtractor circuits based on reversible gates","author":"Kamalakannan","year":"2013","journal-title":"International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/82.486455"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/tcsii.2011.2148970"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2412556"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2018.2832204"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/s00034-020-01559-8"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2019.102961"},{"key":"ref13","first-page":"2250","article-title":"Design and Implementation of 8X8 Truncated Multiplier on FPGA","volume":"3","author":"Rijal","year":"2013","journal-title":"International Journal of Scientific and Research Publications"},{"key":"ref14","first-page":"1","article-title":"Hybrid Binary-Unary Truncated Multiplication for DSP Applications on FPGAs","volume-title":"IEEE International Conference on Computer Aided Design","volume":"38","author":"Rasoul Faraji"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/icmete.2016.79"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/ICCSP.2019.8698112"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378198"},{"key":"ref18","article-title":"An area efficient carry select adder design by sharing the common Boolean logic term","volume-title":"Proceedings of the International Multi Conference of Engineers and Computer Science","volume":"2","author":"Wey"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1049\/rpg2.12760"},{"issue":"10","key":"ref20","first-page":"2789","article-title":"An Efficient Method for Brain Tumor Detection Using Texture Features and SVM Classifier in MR Images","volume":"19","author":"Kavin Kumar","year":"2018","journal-title":"PubMed"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.32604\/csse.2023.033927"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.3233\/jifs-201691"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1149\/10701.12841ecst"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/icjece.2024.3370973"}],"event":{"name":"2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT)","start":{"date-parts":[[2024,6,24]]},"location":"Kamand, India","end":{"date-parts":[[2024,6,28]]}},"container-title":["2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10723818\/10723316\/10723922.pdf?arnumber=10723922","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,27]],"date-time":"2024-11-27T05:42:36Z","timestamp":1732686156000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10723922\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,24]]},"references-count":24,"URL":"https:\/\/doi.org\/10.1109\/icccnt61001.2024.10723922","relation":{},"subject":[],"published":{"date-parts":[[2024,6,24]]}}}