{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,11,28]],"date-time":"2024-11-28T05:23:55Z","timestamp":1732771435229,"version":"3.29.0"},"reference-count":19,"publisher":"IEEE","license":[{"start":{"date-parts":[[2024,6,24]],"date-time":"2024-06-24T00:00:00Z","timestamp":1719187200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,6,24]],"date-time":"2024-06-24T00:00:00Z","timestamp":1719187200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2024,6,24]]},"DOI":"10.1109\/icccnt61001.2024.10726252","type":"proceedings-article","created":{"date-parts":[[2024,11,4]],"date-time":"2024-11-04T23:06:46Z","timestamp":1730761606000},"page":"1-7","source":"Crossref","is-referenced-by-count":0,"title":["Implementation of XOR Gate using AOI model by Reconfigurable Artificial Neural Network on FPGA"],"prefix":"10.1109","author":[{"given":"Sunny","family":"Saini","sequence":"first","affiliation":[{"name":"Bennett University,Dept of Electronics and Communication Engineering,Greater Noida,India"}]},{"given":"Rama S.","family":"Komaragiri","sequence":"additional","affiliation":[{"name":"Bennett University,Dept of Electronics and Communication Engineering,Greater Noida,India"}]},{"given":"Shailesh Singh","family":"Chouhan","sequence":"additional","affiliation":[{"name":"Luleå University of Technology,Cyber Physical System, EISLAB, SRT, Luleå,Luleå,Sweden"}]},{"given":"Mahesh","family":"Kumawat","sequence":"additional","affiliation":[{"name":"Bennett University,Dept of Electronics and Communication Engineering,Greater Noida,India"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/5.58356"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/IJCNN.1999.830886"},{"key":"ref3","first-page":"115","article-title":"Design methodology of a fully parallelized Neural Network on a FPGA","author":"Su\u00e1rez","year":"2013","journal-title":"Recent Adv. Circuits Syst. Signal Process. Commun."},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1142\/S0129065700000156"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1007\/s11220-021-00348-0"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1186\/s40537-021-00461-7"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-021-89005-w"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2920885"},{"issue":"8","key":"ref9","first-page":"88","article-title":"Design artificial neural network using FPGA","volume":"10","author":"Ali","year":"2010","journal-title":"IJCSNS"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/BICTA.2010.5645259"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICFPT47387.2019.00058"},{"article-title":"Zedboard based platform for condition monitoring and control experiments","year":"2018","author":"Adrielsson","key":"ref12"},{"issue":"6","key":"ref13","article-title":"Design and Implementation of BRAM Memory for Reconfigurable Applications","volume-title":"Turkish Online J. Qual. Inq.","volume":"12","author":"Logeswari"},{"key":"ref14","first-page":"1","article-title":"A Low Active Leakage and High-Reliability Phase Storage Element","author":"Memory","year":"2014"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/AIC57670.2023.10263953"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1007\/978-981-16-3199-3"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-42438-5"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1016\/j.procs.2016.05.231"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.32377\/cvrjst2009"}],"event":{"name":"2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT)","start":{"date-parts":[[2024,6,24]]},"location":"Kamand, India","end":{"date-parts":[[2024,6,28]]}},"container-title":["2024 15th International Conference on Computing Communication and Networking Technologies (ICCCNT)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/10723818\/10723316\/10726252.pdf?arnumber=10726252","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,11,27]],"date-time":"2024-11-27T09:37:40Z","timestamp":1732700260000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10726252\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,24]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/icccnt61001.2024.10726252","relation":{},"subject":[],"published":{"date-parts":[[2024,6,24]]}}}