{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T20:31:10Z","timestamp":1730233870726,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.1998.727059","type":"proceedings-article","created":{"date-parts":[[2002,11,27]],"date-time":"2002-11-27T22:03:01Z","timestamp":1038434581000},"page":"258-263","source":"Crossref","is-referenced-by-count":0,"title":["Deep submicron design techniques for the 500 MHz IBM S\/390 G5 custom microprocessor"],"prefix":"10.1109","author":[{"given":"D.E.","family":"Hoffman","sequence":"first","affiliation":[]},{"given":"R.M.","family":"Averill","sequence":"additional","affiliation":[]},{"given":"B.","family":"Curran","sequence":"additional","affiliation":[]},{"given":"Y.H.","family":"Chan","sequence":"additional","affiliation":[]},{"given":"A.","family":"Dansky","sequence":"additional","affiliation":[]},{"given":"R.","family":"Hatch","sequence":"additional","affiliation":[]},{"given":"T.","family":"McNamara","sequence":"additional","affiliation":[]},{"given":"T.","family":"McPherson","sequence":"additional","affiliation":[]},{"given":"G.","family":"Northrop","sequence":"additional","affiliation":[]},{"given":"L.","family":"Sigal","sequence":"additional","affiliation":[]},{"given":"A.","family":"Pelella","sequence":"additional","affiliation":[]},{"given":"P.M.","family":"Williams","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/rd.414.0489"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1147\/rd.414.0515"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ECTC.1997.606264"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1147\/rd.414.0611"},{"key":"ref5","first-page":"247","article-title":"High Performance CMOS Circuit Techniques for The G4 S\/390 Microprocessor","author":"warnock","year":"0","journal-title":"1997 IEEE Intl Conference on Coputer Design"},{"key":"ref8","first-page":"128","article-title":"A 2ns Access, 500MHz 288Kb SRAM Macro","author":"pelella","year":"0","journal-title":"1996 Symposium on VLSI Circuits. Digest of Technical Papers"},{"key":"ref7","first-page":"106","article-title":"Testing the 400MHz IBM G4 CMOS Chip","author":"foote","year":"1997","journal-title":"International Test Conference"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1997.628874"},{"key":"ref9","first-page":"208","article-title":"A 15Kb 1.5ns Access On-Chip Tag SRAM","author":"lu","year":"0","journal-title":"1997 IEEE Intl Symposium in VLSI Tech Sys Applications"},{"key":"ref1","first-page":"168","article-title":"A 400MHz S\/390 Microprocessor","volume":"449","author":"webb","year":"0","journal-title":"1997 IEEE International Solid State Circuit Conference Digest of Technical Papers"}],"event":{"name":"International Conference on Computer Design. VLSI in Computers and Processors","acronym":"ICCD-98","location":"Austin, TX, USA"},"container-title":["Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx4\/5873\/15654\/00727059.pdf?arnumber=727059","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,10]],"date-time":"2017-03-10T07:22:22Z","timestamp":1489130542000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/727059\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/iccd.1998.727059","relation":{},"subject":[]}}