{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T15:28:24Z","timestamp":1729610904134,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.2002.1106750","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T00:51:07Z","timestamp":1056588667000},"page":"70-75","source":"Crossref","is-referenced-by-count":2,"title":["Environment synthesis for compositional model checking"],"prefix":"10.1109","author":[{"given":"H.","family":"Peng","sequence":"first","affiliation":[]},{"given":"Y.","family":"Mokhtari","sequence":"additional","affiliation":[]},{"given":"S.","family":"Tahar","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"article-title":"Compositional Verification for Large Scale Designs: Environment Synthesis and Model Reduction","year":"2002","author":"peng","key":"ref10"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"248","DOI":"10.1007\/10722167_21","article-title":"Efficient Büchi automata from LTL formula","volume":"1855","author":"somenzi","year":"2000","journal-title":"Proceedings of Computer Aided Verification"},{"journal-title":"Specification of a 4*4 ATM switch","year":"1998","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LICS.1995.523248"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/177492.177725"},{"key":"ref3","first-page":"1987","article-title":"Cadence Design Systems","year":"0","journal-title":"Technical manual of FormalCheck v 2 3 edition"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-60218-6_31"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"280","DOI":"10.1007\/3-540-48153-2_21","article-title":"Have I written enough properties? – a method of comparison between specification and implementation","volume":"1703","author":"katz","year":"1999","journal-title":"Proc Correct Hardware Designs and Verification Methods"},{"journal-title":"The Temporal Logic of Reactive and Concurrent Systems Safety","year":"1991","author":"manna","key":"ref8"},{"key":"ref7","first-page":"643","article-title":"The common fragment of ctl and ltl","author":"maidl","year":"2000","journal-title":"41st Annual Symposium on Foundations of Computer Science"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"428","DOI":"10.1007\/3-540-61474-5_95","article-title":"VIS: A system for verification and synthesis","volume":"1102","author":"brayton","year":"1996","journal-title":"Proceedings of Computer Aided Verification"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"538","DOI":"10.1007\/10722167_40","article-title":"FoCs: Automatic generation of simulation checkers from formal specifications","author":"abarbanel","year":"2000","journal-title":"LNCS 1855 Computer Aided Verification"},{"key":"ref9","first-page":"168","article-title":"Assume-guarantee model checking of software: A comparative case study","author":"pasareanu","year":"1999","journal-title":"Proceedings of SPIN Workshop 1999"}],"event":{"name":"2002 IEEE International Conference on Computer Design","acronym":"ICCD-02","location":"Freiberg, Germany"},"container-title":["Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8166\/24311\/01106750.pdf?arnumber=1106750","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,2,25]],"date-time":"2018-02-25T00:33:49Z","timestamp":1519518829000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1106750\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iccd.2002.1106750","relation":{},"subject":[]}}