{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T20:39:10Z","timestamp":1729629550962,"version":"3.28.0"},"reference-count":11,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.2002.1106753","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T00:51:07Z","timestamp":1056588667000},"page":"91-96","source":"Crossref","is-referenced-by-count":0,"title":["High level functional verification closure"],"prefix":"10.1109","author":[{"given":"S.","family":"Dudani","sequence":"first","affiliation":[]},{"given":"J.","family":"Nagda","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1994.331949"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IWRSP.1997.618893"},{"key":"ref10","doi-asserted-by":"crossref","first-page":"296","DOI":"10.1007\/3-540-46002-0_21","article-title":"The For Spec Temporal Logic: A New Temporal Property-Specification Logic","author":"armoni","year":"2002","journal-title":"Proc of Tools and Algorithms for Construction and Analysis of Systems(TACS)"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1999.810714"},{"year":"2002","key":"ref11","article-title":"OpenVera 2.0"},{"key":"ref5","first-page":"120","article-title":"Smart Simulation Using Collaborative Formal and Simulation Engines","author":"ho","year":"2000","journal-title":"Proc Intl Conf on Computer-Aided Design"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2001.955007"},{"key":"ref7","first-page":"456","article-title":"Improved Design Verification by Random Simulation Guided by Genetic Algorithms","author":"faye","year":"2000","journal-title":"Proc of ICDA\/APChDL IFIP World Camp Congress"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337527"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"363","DOI":"10.1007\/3-540-44585-4_33","article-title":"The Temporal Logic Sugar","volume":"2102","author":"beer","year":"2001","journal-title":"Proc Conf Computer-Aided Verification"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/54.936247"}],"event":{"name":"2002 IEEE International Conference on Computer Design","acronym":"ICCD-02","location":"Freiberg, Germany"},"container-title":["Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8166\/24311\/01106753.pdf?arnumber=1106753","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T22:45:37Z","timestamp":1497566737000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1106753\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iccd.2002.1106753","relation":{},"subject":[]}}