{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,14]],"date-time":"2025-05-14T14:27:00Z","timestamp":1747232820504,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.2002.1106754","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:51:07Z","timestamp":1056574267000},"page":"98-103","source":"Crossref","is-referenced-by-count":32,"title":["A 10 Gbps full-AES crypto design with a twisted-BDD S-Box architecture"],"prefix":"10.1109","author":[{"given":"S.","family":"Morioka","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"Satoh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"239","article-title":"A Compact Rijndael Hardware Architecture with S-Box Optimization","volume":"2248","author":"satoh","year":"2001","journal-title":"ASIACRYPT Proceedings LNCS"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2002.1010996"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1986.1676819"},{"key":"ref13","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-3154-8_13","article-title":"AND-EXOR expressions and their optimization","author":"sasao","year":"1993","journal-title":"Logic Synthesis and Optimization"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/EDAC.1993.386463"},{"key":"ref4","first-page":"53","article-title":"Architectural Optimization for a 1.82 Gbits\/sec VLSI Implementation of the AES Rijndael Algorithm","volume":"2162","author":"kuo","year":"2001","journal-title":"proc of CHES LNCS"},{"key":"ref3","first-page":"279","article-title":"Hardware Evaluation of the AES Finalists","author":"ichikawa","year":"2000","journal-title":"Proc Third AES Candidate Conf"},{"key":"ref6","first-page":"68","article-title":"High Performance Single-chip FPGA Rijndael Algorithm Implementations","author":"mcloone","year":"2001","journal-title":"Proc of CHES2001"},{"article-title":"Hardware Performance Simulation of Round 2 Advanced Encryption Standard Algorithm","year":"0","author":"weeks","key":"ref5"},{"key":"ref8","first-page":"342","article-title":"Efficient Algorithms for Elliptic Curve Cryptosystems","volume":"1294","author":"guajardo","year":"1997","journal-title":"Proc of 17th Annual Intl Cryptology Conf (CRYPTO'97) LNCS"},{"key":"ref7","first-page":"81","article-title":"Two Methods of Rijndael Implementation in Reconfigurable Hardware","volume":"2162","author":"fischer","year":"2001","journal-title":"proc of CHES LNCS"},{"year":"0","key":"ref2","article-title":"Advanced Encryption Standard (AES)"},{"article-title":"AES Proposal: Rijndael","year":"0","author":"daemen","key":"ref1"},{"key":"ref9","first-page":"175","article-title":"Efficient Rijndael Encryption Implementation with Composite Field Arithmetic","volume":"2162","author":"rudra","year":"2001","journal-title":"proc of CHES LNCS"}],"event":{"name":"2002 IEEE International Conference on Computer Design","acronym":"ICCD-02","location":"Freiberg, Germany"},"container-title":["Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8166\/24311\/01106754.pdf?arnumber=1106754","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:45:37Z","timestamp":1497552337000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1106754\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/iccd.2002.1106754","relation":{},"subject":[]}}