{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T12:31:10Z","timestamp":1742387470951,"version":"3.28.0"},"reference-count":40,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.2002.1106755","type":"proceedings-article","created":{"date-parts":[[2003,6,26]],"date-time":"2003-06-26T00:51:07Z","timestamp":1056588667000},"page":"104-111","source":"Crossref","is-referenced-by-count":5,"title":["Design of delay-insensitive three dimension pipeline array multiplier for image processing"],"prefix":"10.1109","author":[{"given":"A.","family":"Taubin","sequence":"first","affiliation":[]},{"given":"K.","family":"Fant","sequence":"additional","affiliation":[]},{"given":"J.","family":"McCardle","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2002.1000292"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2002.1000311"},{"key":"ref33","article-title":"Translating Concurrent Communicating Programs into Asynchronous Circuits","author":"brunvand","year":"1991","journal-title":"Technical Report CMU-CS-91–198"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1998.666508"},{"key":"ref31","first-page":"210","author":"koren","year":"1993","journal-title":"Computer Arithmetic Algorithms"},{"key":"ref30","first-page":"188","article-title":"VLSI system design using asynchronous wave pipelines: A 0.35 mu m CMOS 1.5 GHz elliptic curve public key cryptosystem chip","author":"hauck","year":"2000","journal-title":"Proc International Symposium on Advanced Research in Asynchronous Circuits and Systems"},{"key":"ref37","first-page":"61","author":"sobelman","year":"1998","journal-title":"CMOS circuit design of threshold gates with hysteresis In Proc International Symposium on Circuits and Systems"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2000.836983"},{"journal-title":"Theseus Logic TSMC 0 25 Process NCL Flow Standard Cell Library","first-page":"50","year":"2001","key":"ref35"},{"journal-title":"CircuitMaker Integrated Schematic Capture and Circuit Simulation User Manual Protel International Limited","year":"1999","key":"ref34"},{"key":"ref10","first-page":"36","author":"lloyd","year":"2001","journal-title":"A practical comparison of asynchronous design styles In Proc International Symposium on Advanced Research in Asynchronous Circuits and Systems"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.2001.914082"},{"key":"ref11","first-page":"126","author":"cummings","year":"1994","journal-title":"An asynchronous pipelined lattice structure filter In Proc International Symposium on Advanced Research in Asynchronous Circuits and Systems"},{"key":"ref12","first-page":"1244","volume":"47","author":"manohar","year":"1998","journal-title":"Tierno Asynchronous Parallel Prefix Computation IEEE Transactions on Computer-Aided Design"},{"key":"ref13","first-page":"784","author":"parhi","year":"1999","journal-title":"VLSI Digital Signal Processing Systems Design and Implementation"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/BF02252954"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(92)90001-F"},{"journal-title":"The orphans in 2 value NULL convention logic Theseus Logic","year":"1998","author":"fant","key":"ref16"},{"key":"ref17","doi-asserted-by":"crossref","first-page":"149","DOI":"10.1109\/ASYNC.2002.1000305","article-title":"Checking Delay-Insensitivity: Gates and Beyond","author":"kondratyev","year":"2002","journal-title":"International Symposium on Advanced Research in Asynchronous Circuits and Systems"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/IWV.2000.844538"},{"key":"ref19","doi-asserted-by":"crossref","first-page":"247","DOI":"10.1109\/ICCD.2000.878293","article-title":"Tyler Thorp and Carl Sechen Output Prediction Logic","author":"mcmurchie","year":"0","journal-title":"A High-Performance CMOS Design Technique Proceedings of the 2000 IEEE International Conference on Computer Design"},{"key":"ref28","doi-asserted-by":"crossref","first-page":"247","DOI":"10.1049\/ip-cds:19982125","article-title":"design and characterisation of a cmos vlsi self-timed multiplier architecture based on a bit-level pipelined-array structure","volume":"145","author":"acosta","year":"1998","journal-title":"Circuits Devices and Systems IEE Proceedings-"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276286"},{"key":"ref27","first-page":"256","author":"kim","year":"2000","journal-title":"An asynchronous matrix-vector multiplier for discrete cosine transform In International Symposium on Low Power Electronics and Design"},{"journal-title":"Asynchronous Sequential Switching Circuits","year":"1969","author":"unger","key":"ref3"},{"key":"ref6","first-page":"204","author":"muller","year":"1959","journal-title":"A theory of asynchronous circuits In Proceedings of an International Symposium on the Theory of Switchin"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/4.938377"},{"journal-title":"AMULET3 a 100 MIPS asynchronous embedded processor In Proc International Conf Computer Design (ICCD)","year":"2000","author":"furber","key":"ref5"},{"journal-title":"Handshake Circuits An Asynchronous Architecture for VLSI Programming","year":"1993","author":"van berkel","key":"ref8"},{"key":"ref7","first-page":"1","article-title":"Programming in VLSI: From communicating processes to delay-insensitive circuits","author":"martin","year":"1990","journal-title":"Developments in Concurrency and Communication UT Year of Programming Series"},{"journal-title":"MaxVideo 250 Hardware Reference Manual","year":"0","key":"ref2"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ASAP.1996.542821"},{"journal-title":"ImageFlow Technical Description Pipeline Image Processing with ImageFlow White paper Datacube Inc","first-page":"11","year":"1998","key":"ref1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1016\/0167-9260(93)90034-A"},{"key":"ref22","first-page":"149","article-title":"Asynchronous multipliers as combinational handshake circuits","author":"haans","year":"1993","journal-title":"Asynchronous Design Methodologies Volume A-28 of IFIP Transactions"},{"key":"ref21","first-page":"165","article-title":"Design of self-timed multipliers: A comparison","author":"sparso","year":"1993","journal-title":"Asynchronous Design Methodologies Volume A-28 of IFIP Transactions"},{"key":"ref24","first-page":"490","author":"parhami","year":"2000","journal-title":"Computer Arithmetic Algorithms and Hardware Designs"},{"key":"ref23","first-page":"45","article-title":"Self-timed fully pipelined multipliers","author":"salomon","year":"1993","journal-title":"Asynchronous Design Methodologies Volume A-28 of IFIP Transactions"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/92.924058"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ASYNC.1997.587174"}],"event":{"name":"2002 IEEE International Conference on Computer Design","acronym":"ICCD-02","location":"Freiberg, Germany"},"container-title":["Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8166\/24311\/01106755.pdf?arnumber=1106755","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T22:45:37Z","timestamp":1497566737000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1106755\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":40,"URL":"https:\/\/doi.org\/10.1109\/iccd.2002.1106755","relation":{},"subject":[]}}