{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T12:09:21Z","timestamp":1725538161840},"reference-count":11,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.2002.1106767","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:51:07Z","timestamp":1056574267000},"page":"180-186","source":"Crossref","is-referenced-by-count":1,"title":["Balancing the interconnect topology for arrays of processors between cost and power"],"prefix":"10.1109","author":[{"given":"E.Y.","family":"Cheng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Feng Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Bo Yao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chung-Kuan Cheng","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Graham","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/1283920.1283929"},{"journal-title":"Mathematical Theory of Connecting Networks and Telephone Traffic","year":"1965","author":"benes","key":"ref3"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/FPGA.1998.707877"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1002\/j.1538-7305.1953.tb01433.x"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/378239.379048"},{"article-title":"Introduction to Parallel Algorithms and Architectures: Arrays, Trees, Hypercubes","year":"1992","author":"leighton","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/127601.127687"},{"key":"ref7","first-page":"210","article-title":"A diagnoal-interconnect architecture and its applications to RISC core design","author":"igarashi","year":"2002","journal-title":"ISSCC Digest of Technical Papers"},{"key":"ref2","first-page":"5","article-title":"VLSI Theory and Parallel Supercomputing","author":"leiserson","year":"1989","journal-title":"Advanced Research in VLSI Proceedings of the Decennial Caltech Conference on VLSI"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2000.854387"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1985.6312192"}],"event":{"name":"2002 IEEE International Conference on Computer Design","acronym":"ICCD-02","location":"Freiberg, Germany"},"container-title":["Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8166\/24311\/01106767.pdf?arnumber=1106767","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,13]],"date-time":"2017-03-13T18:07:25Z","timestamp":1489428445000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1106767\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iccd.2002.1106767","relation":{},"subject":[]}}