{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:58:05Z","timestamp":1729641485824,"version":"3.28.0"},"reference-count":13,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.2002.1106790","type":"proceedings-article","created":{"date-parts":[[2003,6,25]],"date-time":"2003-06-25T20:51:07Z","timestamp":1056574267000},"page":"327-332","source":"Crossref","is-referenced-by-count":0,"title":["Power analysis of bipartition and dual-encoding architecture for pipelined circuits"],"prefix":"10.1109","author":[{"family":"Shanq-Jang Ruan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Chia-Lin Ho","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Naroska","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Feipei Lai","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","first-page":"84","article-title":"A Bipartition-Codec Architecture to Reduce Power in Pipelined Circuits","author":"ruan","year":"1999","journal-title":"Proceedings of IEEE\/ACM int'L Conf on Computer Aided Design"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1997.621598"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/43.728924"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1999.806520"},{"key":"ref4","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1049\/ip-cds:19990276","article-title":"circuit partitioning algorithm for low-power design under area constraints using simulated annealing","volume":"146","author":"choi","year":"1999","journal-title":"Circuits Devices and Systems IEE Proceedings-"},{"key":"ref3","first-page":"-49v","article-title":"An Entropy-Based Algorithm to Reduce Area Overhead for Bipartition-Codec Architecture","author":"chen","year":"2001","journal-title":"Proc IEEE Int Symp Circuits Syste"},{"key":"ref6","first-page":"398","article-title":"Retiming Sequential Circuits for Low Power","author":"moterio","year":"1993","journal-title":"Proceedings of IEEE\/ACM int'L Conf on Computer Aided Design"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/4.748193"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276316"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/343647.343873"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.364440"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/92.335011"},{"key":"ref9","first-page":"609","article-title":"An Effective Output-Oriented Algorithm for Low Power Multipartition Architecture","author":"ruan","year":"2000","journal-title":"IEEE Int'l Conf on Electronics Circuits and Systems"}],"event":{"name":"2002 IEEE International Conference on Computer Design","acronym":"ICCD-02","location":"Freiberg, Germany"},"container-title":["Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8166\/24311\/01106790.pdf?arnumber=1106790","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,15]],"date-time":"2017-06-15T18:45:38Z","timestamp":1497552338000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1106790\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iccd.2002.1106790","relation":{},"subject":[]}}