{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T02:40:39Z","timestamp":1729651239021,"version":"3.28.0"},"reference-count":23,"publisher":"IEEE Comput. Soc","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.2003.1240917","type":"proceedings-article","created":{"date-parts":[[2004,5,6]],"date-time":"2004-05-06T16:18:03Z","timestamp":1083860283000},"page":"344-349","source":"Crossref","is-referenced-by-count":0,"title":["Interconnect estimation for FPGAs under timing driven domains"],"prefix":"10.1109","author":[{"family":"Parivallal Kannan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"family":"Dinesh Bhatia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Circuits Interconnections and Packaging for VLSI","year":"1990","author":"bakoglu","key":"ref10"},{"key":"ref11","article-title":"Congestion minimization during placement","author":"wang","year":"1999","journal-title":"Proc of the International Symposium on Physical Design (ISPD)"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"326","DOI":"10.1145\/157485.164915","article-title":"on routability prediction for field-programmable gate arrays","author":"chan","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/43.251146"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/92.678873"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.1994.408768"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1137\/0132071"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-2363-2"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TEC.1961.5219222"},{"key":"ref19","article-title":"Automated rip-up and reroute techniques","author":"dees","year":"1982","journal-title":"Proc Design Automation Conference"},{"key":"ref4","article-title":"Why Interconnect Prediction doesnt Work","author":"scheffer","year":"2000","journal-title":"Proc ACM Int Workshop Syst Level Interconnect Prediction (SLIP)"},{"journal-title":"Xilinx Inc","article-title":"Virtex II Platform FPGA Handbook","year":"2001","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1979.1084635"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TCS.1981.1084958"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/369691.369749"},{"key":"ref7","article-title":"RISA: Accurate and efficient Placement Routability Modeling","author":"liang","year":"1994","journal-title":"Proc of ICCAD"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-3572-0"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","article-title":"VPR: A new packing, placement and routing tool for FPGA research","author":"betz","year":"1997","journal-title":"Field-Programmable Logic and Applications"},{"key":"ref9","doi-asserted-by":"crossref","DOI":"10.1007\/3-540-44687-7_5","article-title":"fGREP-Fast Generic Routing demand Estimation for Placed FPGA Circuits","author":"kannan","year":"2001","journal-title":"11th International Workshop on Field-Programmable Logic and Applications FPL"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/201310.201328"},{"key":"ref22","doi-asserted-by":"crossref","DOI":"10.1126\/science.220.4598.671","article-title":"Optimization by simulated annealing","volume":"220","author":"kirkpatrick","year":"1983","journal-title":"Science"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4612-1098-6"},{"key":"ref23","doi-asserted-by":"crossref","DOI":"10.1109\/DAC.2002.1012596","article-title":"On Metrics for Comparing Routability Estimation Methods for FPGAs","author":"kannan","year":"2002","journal-title":"Proc 39th Design Automation Conference"}],"event":{"name":"21st International Conference on Computer Design","acronym":"ICCD-03","location":"San Jose, CA, USA"},"container-title":["Proceedings 21st International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/8790\/27821\/01240917.pdf?arnumber=1240917","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T02:52:17Z","timestamp":1497581537000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1240917\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":23,"URL":"https:\/\/doi.org\/10.1109\/iccd.2003.1240917","relation":{},"subject":[]}}