{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,29]],"date-time":"2024-10-29T20:32:47Z","timestamp":1730233967847,"version":"3.28.0"},"reference-count":34,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.2004.1347916","type":"proceedings-article","created":{"date-parts":[[2004,11,8]],"date-time":"2004-11-08T16:28:24Z","timestamp":1099931304000},"page":"160-167","source":"Crossref","is-referenced-by-count":4,"title":["On-chip transparent wire pipelining"],"prefix":"10.1109","author":[{"given":"M.R.","family":"Casu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Macchiarulo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","article-title":"A methodology for optimal repeater insertion in pipelined interconnects","volume":"32","year":"2003","journal-title":"IEEE TCAD"},{"doi-asserted-by":"publisher","key":"17","DOI":"10.1145\/774572.774609"},{"doi-asserted-by":"publisher","key":"18","DOI":"10.1109\/ICCAD.2002.1167545"},{"doi-asserted-by":"publisher","key":"33","DOI":"10.1145\/502175.502180"},{"key":"15","article-title":"A method for correcting the functionality of a wire-pipelined circuit","author":"sachin","year":"2004","journal-title":"Proc DAC 04"},{"year":"1976","author":"lawvere","journal-title":"Combinatorial Optimization Networks and Matroids","key":"34"},{"key":"16","article-title":"Flip-flop and repeater insertion for early interconnect planning","author":"lu","year":"0","journal-title":"Proc DATE 2002"},{"doi-asserted-by":"publisher","key":"13","DOI":"10.1109\/SBCCI.2003.1232805"},{"key":"14","first-page":"602","article-title":"Architecture-level synthesis for automatic interconnect pipelining","author":"cong","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"doi-asserted-by":"publisher","key":"11","DOI":"10.1109\/ICCAD.2003.159693"},{"key":"12","article-title":"Retiming for wire pipelining in system-on-chip","author":"lin","year":"0","journal-title":"Proc ICCAD 2003"},{"doi-asserted-by":"publisher","key":"21","DOI":"10.1145\/981066.981081"},{"doi-asserted-by":"publisher","key":"20","DOI":"10.1145\/981066.981077"},{"key":"22","first-page":"634","article-title":"Profile-guided microarchitectural floorplanning for deep submicron processor design","author":"ekpanyapong","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"doi-asserted-by":"publisher","key":"23","DOI":"10.1145\/996566.996742"},{"year":"0","key":"24"},{"year":"0","key":"25"},{"doi-asserted-by":"publisher","key":"26","DOI":"10.1109\/92.831439"},{"doi-asserted-by":"publisher","key":"27","DOI":"10.1145\/274535.274546"},{"doi-asserted-by":"publisher","key":"28","DOI":"10.1109\/TVLSI.2004.825851"},{"year":"1999","author":"mcmillan","journal-title":"Getting Started with SMV","key":"29"},{"doi-asserted-by":"publisher","key":"3","DOI":"10.1109\/ICCAD.1999.810667"},{"year":"2001","journal-title":"The International Technology Roadmap for Semiconductors","key":"2"},{"key":"10","article-title":"Interconnect planning with local area constrained retiming","author":"lu","year":"0","journal-title":"Proc DATE 2003"},{"doi-asserted-by":"publisher","key":"1","DOI":"10.1109\/43.898830"},{"year":"0","key":"30"},{"doi-asserted-by":"publisher","key":"7","DOI":"10.1109\/DATE.2004.1269025"},{"key":"6","first-page":"576","article-title":"A new approach to latency insensitive design","author":"casu","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"doi-asserted-by":"publisher","key":"32","DOI":"10.1109\/DATE.2004.1269102"},{"doi-asserted-by":"publisher","key":"5","DOI":"10.1109\/43.945302"},{"key":"31","article-title":"A detailed implementation of latency insensitive protocols","author":"casu","year":"2003","journal-title":"Proc FMGALS 2003"},{"doi-asserted-by":"publisher","key":"4","DOI":"10.1145\/337292.337441"},{"doi-asserted-by":"publisher","key":"9","DOI":"10.1109\/ICCAD.2000.896441"},{"doi-asserted-by":"publisher","key":"8","DOI":"10.1109\/DAC.2001.935470"}],"event":{"name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.","location":"San Jose, CA, USA"},"container-title":["IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9333\/29644\/01347916.pdf?arnumber=1347916","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,15]],"date-time":"2017-03-15T03:10:43Z","timestamp":1489547443000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1347916\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":34,"URL":"https:\/\/doi.org\/10.1109\/iccd.2004.1347916","relation":{},"subject":[]}}