{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:43:43Z","timestamp":1729676623902,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"DOI":"10.1109\/iccd.2004.1347945","type":"proceedings-article","created":{"date-parts":[[2004,11,8]],"date-time":"2004-11-08T11:28:24Z","timestamp":1099913304000},"page":"350-353","source":"Crossref","is-referenced-by-count":1,"title":["Layout driven optimization of datapath circuits using arithmetic reasoning"],"prefix":"10.1109","author":[{"given":"I.","family":"Neumann","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"D.","family":"Stoffel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"K.","family":"Sulimma","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Berkelaar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"W.","family":"Kunz","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2004.1347945"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1145\/337292.337420"},{"key":"14","article-title":"An integrated approach to timing-driven synthesis and placement of arithmetic cirtcuits","author":"shin","year":"0","journal-title":"Proc ASPDAC"},{"key":"11","first-page":"2","article-title":"Perturb and simplify: Multi-level boolean network optimizer","author":"chang","year":"1995","journal-title":"ICCAD-94"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1998.144252"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/12.660163"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/12.485568"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-0817-5"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1994.629735"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2001.922059"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2000.896511"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2001.968621"},{"key":"4","doi-asserted-by":"crossref","first-page":"215","DOI":"10.1109\/12.910813","article-title":"An optimal allocation of carry-save-adders in arithmetic circuits","volume":"50","author":"um","year":"2001","journal-title":"IEEE Trans on Comp"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2004.826548"},{"key":"8","first-page":"31","article-title":"Concurrent logic restructuring and placement for timing closure","author":"lou","year":"1999","journal-title":"Proc ICCAD 1999"}],"event":{"name":"IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings.","location":"San Jose, CA, USA"},"container-title":["IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings."],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/9333\/29644\/01347945.pdf?arnumber=1347945","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,16]],"date-time":"2017-06-16T07:38:39Z","timestamp":1497598719000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/1347945\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[null]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/iccd.2004.1347945","relation":{},"subject":[]}}