{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T23:55:54Z","timestamp":1729641354519,"version":"3.28.0"},"reference-count":35,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006,10]]},"DOI":"10.1109\/iccd.2006.4380805","type":"proceedings-article","created":{"date-parts":[[2007,11,13]],"date-time":"2007-11-13T16:54:59Z","timestamp":1194972899000},"page":"127-133","source":"Crossref","is-referenced-by-count":5,"title":["Dynamic Co-Processor Architecture for Software Acceleration on CSoCs"],"prefix":"10.1109","author":[{"given":"Abhishek","family":"Mitra","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zhi","family":"Guo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Anirban","family":"Banerjee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Walid","family":"Najjar","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"Xilinx CORDIC 3 0 DS 239","year":"0","key":"ref33"},{"journal-title":"The Machine-SUIF Static Single Assignment Library Division of Engineering and Applied Sciences","year":"2002","author":"holloway","key":"ref32"},{"journal-title":"The Machine SUIF Bit-Vector Data-Flow-Analysis Library Division of Engineering and Applied Sciences","year":"2002","author":"holloway","key":"ref31"},{"journal-title":"Machine SUIF Control Flow Graph Library Division of Engineering and Applied Sciences","year":"2002","author":"holloway","key":"ref30"},{"journal-title":"Xilinx FFT v3 2 DS 260","year":"0","key":"ref35"},{"journal-title":"Xilinx Pipelined Divider v 3 0 DS305","year":"0","key":"ref34"},{"key":"ref10","article-title":"PlanAhead Software as a Platform for Partial Reconfiguration","volume":"55","author":"dorairaj","year":"0","journal-title":"Xilinx XCELL Journal Art"},{"key":"ref11","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-45234-8_55","article-title":"A Self-reconfiguring Platform","author":"blodget","year":"2003","journal-title":"International Conference on Field Programmable Logic and Applications (FPL)"},{"journal-title":"Virtex-4 Multi-Platform FPGA","year":"0","key":"ref12"},{"journal-title":"Xilinx Intellectual Property library Logicore","year":"0","key":"ref13"},{"journal-title":"The SUIF Compiler System","year":"2006","key":"ref14"},{"journal-title":"Machine SUIF","year":"2006","key":"ref15"},{"key":"ref16","article-title":"Optimized Generation of Data-path from C Codes for FPGAs, Int. ACM\/IEEE Design","author":"guo","year":"2005","journal-title":"Automation and Test in Europe Conference (DATE 2005)"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/FPL.2005.1515741"},{"key":"ref18","first-page":"44","article-title":"A Reconfigurable Computing Primer","author":"barr","year":"1998","journal-title":"Multimedia Systems Design"},{"journal-title":"Xilinx Development System Reference Guide 8 1i","first-page":"130","year":"0","key":"ref19"},{"journal-title":"Xilinx OPB IPIF specifications DS414","year":"0","key":"ref28"},{"key":"ref4","article-title":"Integrating and Verifying Intellectual Property Blocks using Platform Express and ModetSim","author":"wala","year":"0","journal-title":"MWSCAS05"},{"journal-title":"Xilinx PLB IPIF specifications DS414","year":"0","key":"ref27"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSS.1998.730594"},{"journal-title":"VSIA Virtual Socket Interface Association","year":"0","key":"ref6"},{"key":"ref29","first-page":"1","article-title":"An Interface Methodology for Retargettable FPGA Peripherals","author":"tien-lung","year":"2003","journal-title":"Engineering of Reconfigurable Systems and Algorithms (ERSA)"},{"article-title":"Impact of Intellectual Property Cores on Field Programmable Gate Array Designs","year":"0","author":"shannon","key":"ref5"},{"key":"ref8","article-title":"Complexity and Performance Tradeoffs with FPGA Partial Reconfiguration Interfaces","author":"tan","year":"0","journal-title":"Proc RAW"},{"journal-title":"Signal Proc IP Cores COTS Journal 09\/2003","first-page":"65","year":"0","key":"ref7"},{"key":"ref2","article-title":"PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays FPGAs","author":"horta","year":"0","journal-title":"WUCS-01-13"},{"journal-title":"Two flows for partial reconfiguration module based or difference based","year":"2003","key":"ref9"},{"key":"ref1","article-title":"Accelerating PowerPC Software Applications","author":"pellerin","year":"0","journal-title":"Xilinx Embedded Magazine"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/504914.504917"},{"key":"ref22","article-title":"Interfacing methodologies for IP re-use in Reconfigurable System on-Chip","author":"lee","year":"2003","journal-title":"Proc SPIE Int Microelectronics MEMS and Nanotechnology Symp"},{"journal-title":"SPIRIT consortium","year":"0","key":"ref21"},{"journal-title":"Accelerated System Performance with APU Enhanced Processing","year":"0","author":"ansari","key":"ref24"},{"journal-title":"PowerPC 405 Processor Block Reference Guide UG018","year":"0","key":"ref23"},{"journal-title":"Xilinx Floating point Operator v2 0 Logicore","year":"0","key":"ref26"},{"journal-title":"Xilinx Fast Simplex Link v2 00a","year":"0","key":"ref25"}],"event":{"name":"2006 International Conference on Computer Design","start":{"date-parts":[[2007,10,1]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2007,10,4]]}},"container-title":["2006 International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4380776\/4380777\/04380805.pdf?arnumber=4380805","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,4]],"date-time":"2019-05-04T06:59:37Z","timestamp":1556953177000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4380805\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,10]]},"references-count":35,"URL":"https:\/\/doi.org\/10.1109\/iccd.2006.4380805","relation":{},"ISSN":["1063-6404"],"issn-type":[{"type":"print","value":"1063-6404"}],"subject":[],"published":{"date-parts":[[2006,10]]}}}