{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,3]],"date-time":"2024-09-03T23:22:45Z","timestamp":1725405765356},"reference-count":45,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2006,10]]},"DOI":"10.1109\/iccd.2006.4380824","type":"proceedings-article","created":{"date-parts":[[2007,11,13]],"date-time":"2007-11-13T16:54:59Z","timestamp":1194972899000},"page":"243-250","source":"Crossref","is-referenced-by-count":6,"title":["Power Droop Testing"],"prefix":"10.1109","author":[{"given":"Ilia","family":"Polian","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alejandro","family":"Czutro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sandip","family":"Kundu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bernd","family":"Becker","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"crossref","first-page":"384","DOI":"10.1145\/157485.164941","article-title":"resolving signal correlations for estimating maximum currents in cmos combinational circuits","author":"kriplani","year":"1993","journal-title":"30th ACM\/IEEE Design Automation Conference"},{"year":"1990","author":"abramovici","journal-title":"Digital Systems Testing and Testable Design","key":"ref38"},{"key":"ref33","first-page":"175","article-title":"Constrained ATPG for broadside transition testing","author":"liu","year":"2003","journal-title":"Int'l Symp on Defect and Fault Tolerance in VLSI Systems"},{"doi-asserted-by":"publisher","key":"ref32","DOI":"10.1109\/TEST.2001.966682"},{"key":"ref31","first-page":"928","article-title":"On the generation of scan-based test sets with reachable states for testing under functional operation conditions","author":"pomeranz","year":"2004","journal-title":"Proceedings 41st Design Automation Conference 2004 DAC"},{"doi-asserted-by":"publisher","key":"ref30","DOI":"10.1109\/TEST.2003.1271098"},{"doi-asserted-by":"publisher","key":"ref37","DOI":"10.1147\/rd.104.0278"},{"doi-asserted-by":"publisher","key":"ref36","DOI":"10.1109\/DATE.2006.243927"},{"key":"ref35","first-page":"229","article-title":"Pseudo-functional scan-based bist for delay fault","author":"lin","year":"2005","journal-title":"VLSI Test Symp"},{"doi-asserted-by":"publisher","key":"ref34","DOI":"10.1109\/ASPDAC.2005.1466151"},{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/ICCAD.1999.810664"},{"doi-asserted-by":"publisher","key":"ref40","DOI":"10.1109\/CICC.1996.510549"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/TADVP.2002.806802"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"95","DOI":"10.1109\/VTEST.1999.766652","article-title":"Test generation for ground bounce in internal logic circuitry","author":"chang","year":"1999","journal-title":"VLSI Test Symp"},{"key":"ref13","first-page":"358","article-title":"Test generation for maximizing ground bounce for internal circuitry with reconvergent fan-outs","author":"chang","year":"2001","journal-title":"VLSI Test Symp"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/43.913759"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/92.924055"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/VTS.2005.65"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/TEST.2005.1584011"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/ETW.2003.1231676"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/TR.2003.821937"},{"doi-asserted-by":"publisher","key":"ref28","DOI":"10.1109\/TNS.2003.813129"},{"key":"ref4","first-page":"110","article-title":"Analysis of ground bounce in deep sub-micron circuits","author":"chang","year":"1997","journal-title":"VLSI Test Symp"},{"year":"1998","author":"pecht","journal-title":"Managing Silicon Chip Reliability","key":"ref27"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TEST.2000.894314"},{"key":"ref6","first-page":"34","article-title":"Automatic test pattern generation for crosstalk glitches in digital circuits","author":"lee","year":"1998","journal-title":"VLSI Test Symp"},{"doi-asserted-by":"publisher","key":"ref29","DOI":"10.1109\/92.863624"},{"key":"ref5","article-title":"Testing for circuit marginalities","author":"kundu","year":"2004","journal-title":"Proc Int l Test Synthesis Workshop"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/TEST.2000.894242"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/ATS.2000.893641"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/JSSC.2004.825120"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/TEST.2000.894243"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/DATE.2004.1269036"},{"key":"ref20","first-page":"1406","article-title":"Power supply noise monitor for signal integrity faults","author":"varquez","year":"2004","journal-title":"Design Automation and Test in Europe"},{"doi-asserted-by":"publisher","key":"ref45","DOI":"10.1109\/CICC.1997.606601"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/TEST.2005.1584012"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/VTS.2005.77"},{"doi-asserted-by":"publisher","key":"ref42","DOI":"10.1109\/ICCD.2000.878270"},{"doi-asserted-by":"publisher","key":"ref24","DOI":"10.1109\/TEST.2005.1584044"},{"doi-asserted-by":"publisher","key":"ref41","DOI":"10.1109\/EDTC.1997.582422"},{"doi-asserted-by":"publisher","key":"ref23","DOI":"10.1109\/TEST.2004.1386949"},{"key":"ref44","first-page":"45","article-title":"Effects of delay model on peakl power estimation of VLSI sequential circuits","author":"hsiao","year":"1997","journal-title":"Int'l Conf on CAD"},{"doi-asserted-by":"publisher","key":"ref26","DOI":"10.1109\/TEST.2002.1041766"},{"doi-asserted-by":"publisher","key":"ref43","DOI":"10.1145\/217474.217501"},{"year":"2000","author":"murarka","journal-title":"Copper-Fundamental Mechanisms for Microelectronis Applications","key":"ref25"}],"event":{"name":"2006 International Conference on Computer Design","start":{"date-parts":[[2007,10,1]]},"location":"San Jose, CA, USA","end":{"date-parts":[[2007,10,4]]}},"container-title":["2006 International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4380776\/4380777\/04380824.pdf?arnumber=4380824","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,5,4]],"date-time":"2019-05-04T07:00:00Z","timestamp":1556953200000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4380824\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,10]]},"references-count":45,"URL":"https:\/\/doi.org\/10.1109\/iccd.2006.4380824","relation":{},"ISSN":["1063-6404"],"issn-type":[{"type":"print","value":"1063-6404"}],"subject":[],"published":{"date-parts":[[2006,10]]}}}