{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,11]],"date-time":"2026-06-11T16:13:29Z","timestamp":1781194409924,"version":"3.54.1"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,10]]},"DOI":"10.1109\/iccd.2007.4601893","type":"proceedings-article","created":{"date-parts":[[2008,8,21]],"date-time":"2008-08-21T11:14:39Z","timestamp":1219317279000},"page":"144-151","source":"Crossref","is-referenced-by-count":1,"title":["FPGA global routing architecture optimization using a multicommodity flow approach"],"prefix":"10.1109","author":[{"given":"Yuanfang","family":"Hu","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yi","family":"Zhu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Michael B.","family":"Taylor","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Chung-Kuan","family":"Cheng","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1155\/1996\/45983"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref10","article-title":"SIS: A System for Sequential Circuit Analysis","author":"sentovich","year":"1992"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.827562"},{"key":"ref11","article-title":"Logic Synthesis and Optimization Bench-marks, Version 3.0","author":"yang","year":"1991"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/43.273754"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1147058"},{"key":"ref7","first-page":"111","article-title":"Physical Synthesis of Energy-Efficient NoCs Through Topology Exploration and Wire Style Optimization","author":"hu","year":"2005","journal-title":"International Conference on Computer Design"},{"key":"ref2","doi-asserted-by":"crossref","first-page":"213","DOI":"10.1007\/3-540-63465-7_226","article-title":"VPR: A New Packing, Placement and Routing Tool for FPGA Research","author":"betz","year":"1997","journal-title":"International Workshop on Field-Programmable Logic and Applications"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/1059876.1059881"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/332357.332368"}],"event":{"name":"2007 25th International Conference on Computer Design ICCD 2007","location":"Lake Tahoe, CA, USA","start":{"date-parts":[[2007,10,7]]},"end":{"date-parts":[[2007,10,10]]}},"container-title":["2007 25th International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4591423\/4601871\/04601893.pdf?arnumber=4601893","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T07:08:15Z","timestamp":1497769695000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4601893\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,10]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/iccd.2007.4601893","relation":{},"subject":[],"published":{"date-parts":[[2007,10]]}}}