{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,19]],"date-time":"2025-03-19T11:22:10Z","timestamp":1742383330787},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,10]]},"DOI":"10.1109\/iccd.2007.4601961","type":"proceedings-article","created":{"date-parts":[[2008,8,21]],"date-time":"2008-08-21T15:14:39Z","timestamp":1219331679000},"page":"615-622","source":"Crossref","is-referenced-by-count":3,"title":["Power reduction of chip multi-processors using shared resource control cooperating with DVFS"],"prefix":"10.1109","author":[{"given":"Ryo","family":"Watanabe","sequence":"first","affiliation":[]},{"given":"Masaaki","family":"Kondo","sequence":"additional","affiliation":[]},{"given":"Hiroshi","family":"Nakamura","sequence":"additional","affiliation":[]},{"given":"Takashi","family":"Nanya","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"article-title":"Pentium M hits the street","year":"2003","author":"krewell","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2006.24"},{"journal-title":"SPEC CPU2000","year":"0","key":"ref12"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2002.995703"},{"key":"ref4","first-page":"83","article-title":"Wattch: a framework for architectural-level power analysis and optimizations","author":"brooks","year":"2000","journal-title":"Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat No RS00201) ISCA"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/2.982917"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/4.126534"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2005.27"},{"key":"ref8","doi-asserted-by":"crossref","first-page":"197","DOI":"10.1145\/280756.280894","article-title":"Voltage scheduling problem for dynamically variable voltage processors","author":"ishihara","year":"1998","journal-title":"Proceedings 1998 International Symposium on Low Power Electronics and Design (IEEE Cat No 98TH8379) LPE"},{"journal-title":"H 264\/AVC Reference Software","year":"0","key":"ref7"},{"journal-title":"Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Datasheet","year":"0","key":"ref2"},{"journal-title":"AMD Athlon 64 Processor Power and Thermal Data Sheet","year":"0","key":"ref1"},{"key":"ref9","first-page":"111","article-title":"Fair cache sharing and partitioning in a chip multiprocessor architecture","author":"kim","year":"2004","journal-title":"13th PACT"}],"event":{"name":"2007 25th International Conference on Computer Design ICCD 2007","start":{"date-parts":[[2007,10,7]]},"location":"Lake Tahoe, CA, USA","end":{"date-parts":[[2007,10,10]]}},"container-title":["2007 25th International Conference on Computer Design"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/4591423\/4601871\/04601961.pdf?arnumber=4601961","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,18]],"date-time":"2017-06-18T11:08:16Z","timestamp":1497784096000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/4601961\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,10]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/iccd.2007.4601961","relation":{},"subject":[],"published":{"date-parts":[[2007,10]]}}}